Astro speeds design closure for Sonet/SDH framer

Agere Systems has taped out its newest Sonet/SDH framer SoC using Synopsys' Astro physical implementation solution.

Agere Systems has taped out its newest Sonet/SDH framer SoC using Synopsys' Astro physical implementation solution.

The Agere Mars universal framer IC is the industry's most integrated, full-featured and versatile framer for multiservice metro and access networks - scalable from rates of 155Mbit/s to 10Gbit/s.

The chip is composed of 11 million gates, multiple high-speed interfaces and several hundred clock domains with a system clock speed of 155MHz.

The design was implemented in Agere's leading-edge 140nm silicon process.

Astro, a cornerstone product in Synopsys' complete RTL-to-GDSII solution, played a critical role in the completion of the chip by providing fast, highly efficient placement, routing and advanced physical optimisations.

In addition, Astro is part of Agere's standard ASIC SoC design flow.

"Astro was vital to achieving tape out for this complex design on a tight schedule", said Jim Stefany, Development Director of Optical Networking Integrated Circuits at Agere.

"Astro provided an excellent mix of usability and advanced capabilities, including comprehensive crosstalk prevention and correction, enabling us to efficiently close the design with correct timing, signal integrity and process rules".

For this design, Agere Systems benefited from the full scope of the complete Synopsys RTL-to-GDSII solution - the industry's most complete solution with best-in-class technology for each design phase.

Agere's design flow included Synopsys' Design Compiler family for RTL synthesis, PrimeTime for full-chip static timing analysis, Astro for physical implementation, Star-RCXT for extraction and Hercules for physical verification.

This familiar, trusted and production-proven design tool environment was central to achieving high productivity for Agere.

"In today's environment, our customers' focus is increasingly turning to productivity where design turnaround time is at a premium", said Sanjiv Kaul, Senior Vice President of Corporate Applications and Marketing at Synopsys.

"Agere's SoC tapeout is a great example of Astro's streamlined, easy-to-use, highly productive environment that meets designer needs for fast turnaround".

Astro is the most advanced physical implementation solution for designs at 130nm and below.

Astro extends the foundation of Apollo, Synopsys' 180nm place and route solution.

This common design environment, user interface and Milkyway database access, makes it easy for Apollo users to migrate to Astro for better performance, higher productivity, built-in signal integrity and advance process rule support.

Today, Astro is in use at nine of the world's top 10 semiconductor companies.

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