Product category:
Design and Development Software
News Release from: Synopsys | Subject: SoCBIST
Edited by the Electronicstalk Editorial
Team on 05 March 2003
Test solution aids core-based design
development
Synopsys has added a comprehensive test automation solution for core-based designs to its DFT Compiler, a key component of the Galaxy design platform.
Synopsys has added a comprehensive test automation solution for core-based designs to its DFT Compiler, a key component of the Galaxy design platform The SoCBIST test solution comes with strong industry support from ARM, Agilent and STMicroelectronics and is based on the IEEE P1450.6 core test language (CTL) standard
This article was originally published on Electronicstalk on 2 Oct 2002 at 8.00am (UK)
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"Synopsys and ARM have worked closely together to enable a core test re-use solution for the ARM1136JF-S core, which will significantly reduce our customers' test development costs.
The ARM-Synopsys reference methodology supports this innovative and effective SoC test solution, and ARM will provide test re-use optimised cores, test data and CTL models to help our customers simplify their SoC test challenges.
Designers throughout the industry will benefit from this new standards-based approach to test for core-based designs".
The integration and verification of test in complex multimillion-gate SoCs poses formidable challenges for designers today.
Integrating the design-for-test (DFT) structures of IP cores at the SoC level is difficult and time-consuming, and automatic test pattern generation (ATPG) at the SoC level can expose test problems late in the design process, slowing time to production.
Synopsys' SoC test automation solution addresses these challenges by automating the creation and integration of IP cores that are optimised for test re-use.
First, DFT Compiler automatically synthesises test re-use IP cores, and creates IEEE P1450.6 CTL test models for them.
Next, TetraMAX ATPG generates reusable test patterns for these cores with high fault coverage.
Finally, Synopsys' SoCBIST product reads the CTL models of these cores and automatically integrates the cores into the overall SoC, reusing presupplied core test patterns referenced from the SoC-level pattern set.
In this way, DFT Compiler, TetraMAX ATPG and SoCBIST work together to automate test re-use in IP core-based designs within the Synopsys implementation platform.
"ST designs SoCs for a wide range of applications - from wireless devices to set-top-boxes and other consumer applications.
To help manage the rapidly growing complexity of SoC test within our design flows, we require a standardised IP test methodology across all of our design groups", said Sylvain Kritter, HCMOS Design Platform Director, STMicroelectronics' Central R and D.
"We partnered with Synopsys to create a standards-based SoC test automation solution that would enable us to deploy a streamlined test methodology and enable our designers to achieve significant productivity gains.
As an ARM partner, we are very happy to see this SoC test automation solution included in the ARM Synopsys reference methodology.
We believe this approach will provide ST with the fastest and most comprehensive approach to test implementation for our ARM -based designs".
"Agilent, Synopsys, and ST Micro are leading the industry in development of IEEE P1450.6 CTL-based links between the EDA and ATE environments.
This standards-based solution provides automation of SoC design-to-test, and is expected to dramatically reduce the time needed to develop test programs, making an order of magnitude improvement in time to market possible", said Tom Newsom, Vice President and General Manager of Agilent's SOC Test Business Unit.
"With this capability, we can offer great time-to-market value to our customers by taking core test data directly from the design environment and providing optimised test development for the 93000 SoC Series test platform.
We are very happy to be working with Synopsys, ARM and ST Micro, leaders in their respective markets of EDA, semiconductor IP and semiconductor products, to leverage the emerging CTL standard to enable a superior customer solution".
"Synopsys' customers are challenged with reducing their cost of test while improving product quality and achieving faster time to market", said Antun Domic, Senior Vice President and General Manager, Synopsys Nanometer Analysis and Test business unit.
"Our DFT Compiler SoCBIST product addresses these challenges and integrates seamlessly within the Galaxy Design Platform.
We have further extended the capabilities of our DFT Compiler SoCBIST to automate test re-use for our customers' IP core-based design flows, which we now offer with strong support from world-class companies such as ARM, ST Microelectronics and Agilent".
SoCBIST is an addon option to DFT Compiler, and is available with the March 2003 production release.
Pricing for DFT Compiler SoCBIST begins at US $175,000 list for a one-year technology subscription licence (TSL).
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