Product category:
Design and Development Software
News Release from: Synopsys | Subject: Galaxy Design Platform
Edited by the Electronicstalk Editorial
Team on 05 June 2003
Tools form basis of TSMC Reference Flow
The Galaxy Design Platform and other Synopsys tools have been integrated into TSMC's advanced Reference Flow 4.0.
The Galaxy Design Platform and other Synopsys tools have been integrated into TSMC's advanced Reference Flow 4.0 The TSMC Reference Flow version 4.0 targets designs implemented in TSMC's 130nm and Nexsys 90nm process technologies, and addresses design issues such as signal integrity (SI) closure, multithreshold voltages and design for manufacturability (DFM) rules
This article was originally published on Electronicstalk on 5 Feb 2003 at 8.00am (UK)
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Reference Flow 4.0 is the result of a long-standing collaboration between TSMC and Synopsys in developing proven flows that provide mutual customers with higher productivity and better design quality.
"TSMC and Synopsys have been working together since the release of the TSMC Reference Flow 1.0 about three years ago", said Genda Hu, Vice President of Corporate Marketing at TSMC.
"This latest collaboration has produced a comprehensive offering that uses Synopsys' RTL to GDSII tools to solve complex 90nm design issues and tradeoffs between speed and leakage power.
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Design platform takes on signal integrity tool
Galaxy SI is a new and complete signal integrity solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration.
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Agere Systems has used Synopsys' Galaxy design platform to tape out its 5G APP550 network processor in a 0.13-micron process.
The result is a proven method that manages nanometre-scale design risks and delivers faster time to volume when used in conjunction with TSMC's advanced process technologies".
The TSMC Reference Flow provides powerful timing and SI closure using physical synthesis and physical optimisation technology within Galaxy SI.
Galaxy SI is a complete signal integrity solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration.
Galaxy SI provides designers with a more comprehensive SI solution that includes prevention, analysis, and repair, speeding SI closure for 130nm designs and below.
"By working together, Synopsys and TSMC have provided an environment where customers can be assured of a smoother path to tape out for aggressive, complex designs", said Paul Platt, Vice President of Design Services at IDT.
"IDT is a long-time customer of both companies and recently used Synopsys' Astro and Hercules to successfully tape out a 90nm test chip using TSMC's advanced silicon process.
With Synopsys' and TSMC's collaboration, we were able to design a complex, silicon device for TSMC's process".
The Reference Flow 4.0 provides a solution for addressing DFM rules for the 90nm process, including process variation modelling, metal over via/contact enclosure, redundant via insertion, dummy OD/Poly/Metal insertion and modelling of shallow trench isolation (STI), and length of diffusion (LOD) effects - all of which are becoming critical to improving wafer yield.
Synopsys' Astro provides support for 90nm design rules to address the critical DFM requirements.
Hercules, Star-RCXT, and HSpice handle the RC extraction, LVS and simulation of STI LOD effects.
The Reference Flow 4.0 also addresses leakage power optimisation, based on multi-Vt core cell libraries using Synopsys' Design Compiler, Power Compiler and Physical Compiler tools.
"TSMC's leading process technologies have been driving the most advanced flow requirements.
Synopsys and TSMC's ongoing collaboration has resulted in silicon-proven methodologies that help manage the most critical design risks for complex systems on chip", said Rich Goldman, Vice President of Strategic Market Development at Synopsys.
"Our leading-edge customers look to us to jointly develop future flows and to proactively anticipate and solve new design implementation challenges that enable faster time to tape out for our customers".
The TSMC 4.0 reference flow is available immediately.
The TSMC 4.0 reference flow provides a complete RTL-to-GDSII solution and includes Synopsys' Design Compiler, Physical Compiler, Astro, Astro-Rail, Astro-Xtalk, Floorplan Compiler, DFT Compiler, TetraMAX, VCS, Power Compiler, Star-RCX, PrimeTime, PrimeTime SI, Hercules and HSpice.
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