Design platform takes on signal integrity tool

Galaxy SI is a new and complete signal integrity solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration.

Galaxy SI is a new and complete signal integrity (SI) solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration.

Galaxy SI provides designers with comprehensive prevention, analysis and sign-off, speeding SI closure for 130-nanometre designs and below.

"We used Galaxy SI in our Unicad design environment for signal integrity prevention and sign-off of our 120-nanometre production designs, and have now adopted the solution for our next-generation 90-nanometre designs", said Jean-Pierre Geronimi, Director of Computer Aided Design, STMicroelectronics Research and Development.

"Synopsys' Galaxy SI offers the most complete signal integrity solution available for designers today, integrates readily into our flow, and speeds timing and SI closure".

Existing SI solutions are incomplete in that they offer a mix of point tools or they rely on third-party signoff, which can result in delayed SI closure, or even worse, silicon failure.

In contrast, Synopsys' Galaxy SI solution provides an integrated platform with comprehensive SI support at all stages of the design flow, from implementation to signoff.

Galaxy SI uses PrimeTime's golden delay calculator and common design infrastructure - common libraries, constraints, and database to ensure consistent timing and SI analysis throughout the design flow.

This enables designers to progressively eliminate problems as they move from design planning to placement to routing and signoff, resulting in faster SI closure.

Galaxy SI is easy to adopt because it is built into the Galaxy Design Platform.

All of Galaxy SI's capabilities are integrated into proven tools, within the platform, which are already the foundation of many customers' design environments.

Customers can tape out with confidence, because signoff in Galaxy SI is based on PrimeTime, the industry's most pervasive full-chip static timing signoff solution.

"The challenges presented by designs at 130 nanometres and below demanded a new solution and approach to ensure timing and SI convergence", said Don Friedberg, Director of Design Methodologies at Agere Systems.

"Using Synopsys' Astro, part of the new Galaxy SI solution to prevent and repair crosstalk-induced problems during place and route, we have achieved first-pass SI success on our multi-million-gate 130 nanometre designs".

"TSMC first qualified Synopsys' signal integrity tool suite to enhance the process-specific design methodology for our 130nm and Nexsys 90nm process technologies last October", said Ed Chen, Director of Design and E-Service Marketing at TSMC.

"The highly-integrated signal integrity prevention and analysis capability has been included in TSMC Reference Flow Release 4.0 which is announced today.

We expect our customers who take advantage of this capability to achieve rapid timing and SI closure of their SoC designs".

"To overcome the challenges we faced with our earlier chips, we were looking for an SI solution that complemented our current tool investment", said Henrik Pallisgaard, Director of Product Development, Ethernet Products Group, Vitesse Semiconductor Corp.

"Synopsys' Galaxy SI solution provided us with a comprehensive set of capabilities to analyse and prevent crosstalk throughout our flow.

On a recent design, we were able to achieve chip-level timing in less than four weeks.

We have already achieved first-pass silicon success with Galaxy SI and, as a result, have adopted it into our flow".

"Synopsys continues to enhance the Galaxy Design Platform to address our customers' critical design challenges", said Sanjiv Kaul, Senior Vice President, Corporate Applications and Marketing, Synopsys.

"The adoption of Galaxy SI demonstrates the comprehensiveness of the SI solution we offer, and our customers' confidence in the platform".

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