Renesas improves its design closure time by 30%

Renesas Technology Corp has standardised on the Synopsys Astro physical implementation solution to tape out multiple chips for audio-visual, mobile phone and office automation products.

Renesas Technology Corp has standardised on the Synopsys Astro physical implementation solution to tape out multiple chips for audio-visual, mobile phone and office automation products.

The chips contained up to five million gates with a system clock speed of 400MHz and were implemented in Renesas' advanced 150nm silicon process.

Astro, a cornerstone product in Synopsys' Galaxy design platform and the successor to Synopsys' Apollo place and route product, enabled Renesas to achieve an average of 30% reduction in turnaround time from its previous solution and has become part of Renesas' standard SoC design flow "By using Astro, we were able to achieve silicon success for our complex designs on a very tight schedule", said Hisaharu Miwa, Department Manager of the EDA Technology Development Department at Renesas.

"Our migration from Apollo to Astro was very easy because of the identical data model and user environment between the tools.

Astro runs faster, handles bigger designs and brings about complete design closure, including timing and signal integrity, essential for improved productivity in our leading-edge designs.

In some cases we have seen the design turnaround time reduced by as much as 50%".

Renesas Technology benefits from the full scope of Synopsys' Galaxy Design Platform at each step of their design process.

Renesas' design flow includes Synopsys' Design Compiler family for RTL synthesis, PrimeTime for full-chip static timing analysis, Astro for physical implementation, Star-RCXT for full chip parasitic extraction and Hercules for physical verification.

This familiar, trusted and production-proven design tool environment is central to achieving high productivity for Renesas.

"We are well aware that our customers' focus is increasingly turning to design productivity where design turnaround time is at a premium", said Dr Antun Domic, Senior Vice President and General Manager of the IC Implementation business unit at Synopsys.

"Renesas' use of Astro in their standard flow exemplifies Astro's streamlined, easy-to-use, highly productive environment that meets designer needs for fast turnaround".

Astro is the most advanced physical implementation solution for ultra deep-submicron designs.

Astro extends the foundation of Apollo, Synopsys' 180nm place and route solution.

This common design environment between Apollo and Astro, which includes the user interface and Milkyway database access, makes it easy for Apollo users to migrate to Astro for better performance, higher productivity, built-in signal integrity analysis and advance process rule support.

Today, Astro is in use at the world's top 10 semiconductor companies.

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