Platform to demonstrate PCI Express compatibility

Rambus and Synopsys are to develop a hardware platform that demonstrates the interoperability of their PCI Express IP solutions.

Rambus and Synopsys are to develop a hardware platform that demonstrates the interoperability of their PCI Express IP solutions.

Rambus is providing the RaSer PHY for PCI Express applications, and Synopsys is providing the DesignWare PCI Express endpoint controller core.

Synopsys and Rambus expect to demonstrate a working PCI Express solution that provides seamless operation and lower-risk implementation for chip developers at the PCI Express Interoperability Workshop in the fourth quarter of 2003.

"Synopsys, the market leader in connectivity IP, works closely with leading PHY suppliers, like Rambus, to bring our collaborative solution to compliance testing workshops and demonstrate interoperability", said Guri Stark, Vice President of Marketing, Synopsys Solutions Group.

"By demonstrating interoperability and our advanced verification procedures, we can demonstrate the high quality of our PCI Express IP and reduce risk for our customers that are planning to use the joint solution".

"With this platform, system developers can be assured that they are using IP cells that are proven to interoperate across the PCI Express protocol stack and with other PCI Express systems", said Jean-Marc Patenaude, Marketing Director of the Logic Interface Division at Rambus.

"Rambus has already delivered fully verified silicon supporting the PCI Express interface - our decade-long experience in solving high-speed I/O problems continues to be of great benefit to our customers, who now face the challenge of migrating their 66MHz PCI designs to new 2.5GHz PCI Express solutions".

The platform demonstration will consist of two boards: a motherboard, constructed by Synopsys, using FPGAs to house the Synopsys endpoint controller with driver software, and a daughterboard consisting of Rambus' PHY IP.

The interface between the two boards will adhere to the industry-standard PIPE (PHY Interface for PCI Express) specifications.

Synopsys' motherboard will include three critical protocol layers (the logical PHY layer, the data link layer and the transaction layer), while Rambus' daughterboard will include the analogue PMA (physical media attachment) sublayer and the PCS (physical coding sublayer).

Rambus is committed to continuing its leadership position as a PCI Express PHY IP provider.

Rambus' PCI Express IP PHY family supports TSMC 0.13-micron and UMC 0.18-micron processes to address needs of graphics, chipset, switch and bridge chip applications using the PCI Express standard.

The Rambus PCI Express PHY cell is available in evaluation chips that have been delivered to Rambus' customers for their system development.

In addition, Rambus offers its customers engineering services for chip integration, package, board and system characterisation and test in order to ensure success in the development and bring up of PCI Express-based chips and boards.

The Synopsys DesignWare PCI Express endpoint controller core features configurability from one to eight channels, low gate count and timing closure to a 0.18-micron generic process.

This architecture not only supports all of the features required for a PCI Express Endpoint solution, but it is also optimised for layout and performance and implements "enhanced" transaction layer features.

Back to top