Pair to promote PCI Express interoperability

Synopsys is working with Artisan Components to develop a hardware platform that validates the interoperability of their PCI Express IP solutions.

Synopsys is working with Artisan Components to develop a hardware platform that validates the interoperability of their PCI Express IP solutions.

The platform will conform to the PIPE (PHY Interface for PCI Express) standard and help to assure seamless operation and lower-risk implementation for chip developers.

Synopsys and Artisan plan to develop a mother/daughterboard platform using Synopsys' DesignWare PCI Express endpoint controller core and Artisan's PCI Express PHY IP.

Synopsys and Artisan plan to present the solution at the PCI Express Interoperability Workshop in the fourth quarter of 2003.

"High-speed serial interface PHYs are complex circuits that must be verified both in silicon and in a system context", states Callan Carpenter, Vice President and General Manager, Artisan Analogue/Mixed Signal Business Unit.

"By working together to rigorously establish interoperability between our respective IP, Artisan and Synopsys are helping to reduce the integration risk that confronts every system-on-chip design".

"As the market leader in connectivity IP, Synopsys works with leading PHY suppliers like Artisan to validate interoperability", said Guri Stark, Vice President of Marketing, Synopsys Solutions Group.

"This reduces the risk for designers and gives them the confidence to use our joint solutions in their designs, enabling them to bring products to market more quickly".

The platform demonstration will consist of two boards: a Synopsys-developed motherboard including FPGAs to house the Synopsys endpoint controller with driver software, and a daughterboard consisting of Artisan's PHY silicon.

The interface between the two boards will adhere to industry-standard PIPE specifications.

Synopsys' motherboard will include three critical protocol layers - the logical PHY layer, the data link layer and the transaction layer.

Artisan's daughterboard will include a complete serial link including mux/demux, 8b/10b encode/decode, elastic buffer and clock recovery circuitry that will be compliant with the PCI Express Base 1.0a Specification.

Testability features for the Artisan daughterboard include built-in self-test (BIST), serial and parallel loopbacks, IDDQ (power down) and pseudorandom bit sequence (PRBS).

The Synopsys DesignWare PCI Express endpoint controller core features configurability from one to eight channels, low gate count, and timing closure to a 0.18-micron generic process.

This architecture not only supports all of the features required for a PCI Express endpoint solution, but it is also optimised for layout and performance and implements "enhanced" transaction layer features.

Artisan's PCI Express 2.5Gbit/s PHY core provides high performance, flexibility, low power consumption, and extensive testability within a small physical size.

The PCI Express is a modular design that allows for one- to 32-lane configurations to enable a broad range of computing and communication applications, emphasising performance, cost and scalability.

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