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News Release from: Synopsys | Subject: SystemVerilog technical seminars
Edited by the Electronicstalk Editorial
Team on 19 January 2004
Learn all about SystemVerilog for free
Four leaders in advanced design and verification technologies are sponsoring free SystemVerilog technical seminars and product demonstrations in Israel, Germany, the UK and Japan.
Following the successful North American seminar tour attended by 1000 engineers, four leaders in advanced design and verification technologies - Synopsys, Novas Software, Mentor Graphics and Axis Systems, with the support of Hewlett Packard's platform technology - are sponsoring additional free SystemVerilog technical seminars and product demonstrations in Israel, Germany, the UK and Japan beginning on 2nd February 2004 Each seminar will be presented by noted hardware description language (HDL) expert, Cliff Cummings, President of Sunburst Design
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The "SystemVerilog now!" technical seminars provide design and verification engineers with practical and up-to-date information about SystemVerilog's capabilities.
The seminars demonstrate how these capabilities can translate into increased productivity and silicon success using design and verification tools that support SystemVerilog today.
These productivity gains are equally applicable to VHDL and Verilog-based design and verification flows.
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"Many of the 'SystemVerilog now!' seminar attendees have reinforced the need to unify their design and verification solutions", said Manoj Gandhi, Senior Vice President and General Manager, Verification Group at Synopsys.
"Synopsys plans to address these needs by delivering a unified design and verification platform based on SystemVerilog to enable a comprehensive design-for-verification methodology.
This platform is expected to leverage SystemVerilog's advanced language capabilities for more concise RTL design and comprehensive assertions, and testbench features for streamlined verification".
"The 'SystemVerilog now!' seminars provide the additional training that users have been requesting", said Scott Sandler, President and CEO, Novas Software.
"SystemVerilog holds great promise for methodology improvement across a range of applications.
Driven by our customers' requests for a universal debug platform for design, testbench and assertion languages, Novas has extended its debug automation technology to support SystemVerilog models, allowing for the fast detection and repair of complex issues in designs that leverage these powerful language capabilities".
As an emerging open and public standard, SystemVerilog offers a comprehensive foundation to improve the overall verification process to help alleviate issues with design complexity for the Verilog and VHDL user.
Overall, SystemVerilog offers both the right technology and the broad industry acceptance needed to accelerate design and verification processes while offering greater certainty of silicon success.
"There is a strong interest among engineers to apply SystemVerilog to their next designs", said Robert Hum, Vice President and General Manager of Mentor's Design Verification and Test division.
"The single largest design bottleneck electronics designers face today is design verification.
Mentor Graphics has a strong history of support for open and public standards that permit design teams to craft methodologies that utilise a broad range of verification solutions to solve this critical issue".
"New capabilities in SystemVerilog could have the most impact on engineer's design and verification efforts", said Steve Wang, cofounder, Axis Systems.
"The power of Axis' RCC (reconfigurable computing) technology is demonstrated again with our ability to support SystemVerilog.
Based on customer demand, Axis is working to provide the ability to leverage SystemVerilog constructs to accelerate testbench and assertions in our foremost design team emulation products".
Verilog language extensions are presented in a designer-centric fashion by one of the industry's leading HDL experts, Cliff Cummings.
This highly technical event demonstrates how SystemVerilog can be practically used by both Verilog and VHDL design and verification engineers with immediate benefit to improve design engineering productivity, speed verification and deliver smarter verification.
The "SystemVerilog now!" technical seminar dates and locations are: 2nd February 2004 ib Herzliya, Israel; 4th February in Munich, Germany; 5th February in Reading, UK; and March 2004 in Tokyo, Japan.
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