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Product category: Design and Development Software
News Release from: Synopsys | Subject: PrimeTime
Edited by the Electronicstalk Editorial Team on 13 February 2004

Timing analyser speeds through large SoC
designs

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The new release of PrimeTime has set a new performance standard for static timing analysis and sign-off of 90nm designs, enabling timing analysis of 100-million gate designs.

The new release of PrimeTime has set a new performance standard for static timing analysis and sign-off of 90nm designs, enabling timing analysis of 100-million gate designs Customer benchmarks show an average of three times runtime improvement and up to three times data capacity improvement over the previous release

PrimeTime's significant performance gains are the result of algorithmic improvements in reporting and advanced static timing analysis, combined with a new save-and-restore capability that enables concurrent timing analysis of large, complex designs.

"Fast, accurate static timing analysis that is capable of modeling 90-nanometre effects is essential to our sign-off flow", said Kazuyuki Miyata, Group Manager, Solution Service Group, EDA Technology Development Department, Design Solution Division, Toshiba Microelectronics Corp.

"Synopsys newest version of PrimeTime delivered huge performance gains, especially when modeling manufacturing process variation effects.

These improvements enabled us to verify our latest 11-million gate 90-nanometre design in just three and a half hours, reducing our overall signoff time by 50%".

"We adopted the latest release of PrimeTime to tape out our recent five-million gate system-on-chip design with first-pass silicon success", said Akio Nakajima, Design Manager, Design Systems Development Group, System-on-a-Chip Design Division, NEC Micro Systems.

"The latest PrimeTime release runs three-to-five times faster and uses up to a third less memory than previous releases.

With these improvements, we can now verify large designs on a 32bit Linux machine while reducing our overall timing verification time by half".

PrimeTime (version 2003.12) delivers new capabilities that further improve performance, memory usage and productivity.

A new save-and-restore feature delivers significant productivity improvements, enabling users to restart large timing analysis runs, avoiding lengthy recomputation of data, and enabling concurrent analysis by a design team.

In addition, enhancements made to report generation and to on-chip variation (OCV) analysis with clock re-convergence pessimism removal (CRPR) dramatically speed runtime and data capacity, enabling designers to complete static timing analysis of complex 90nm designs in significantly less time.

"As a leading manufacturer of complex SoCs for wireless and digital consumer applications, Renesas Technology must meet very aggressive market windows", said Hisaharu Miwa, Department Manager, EDA Technology Development Department, Design Technology Division, LSI Product Technology Unit, Renesas Technology Corp.

"Using the new PrimeTime to accurately model process variation effects, we realized four-times runtime and two-times data capacity improvement on our latest 10-million gate SoCs".

"At 90 nanometres and below, advanced static timing analysis features that accurately model silicon behaviour are essential", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.

"Used as an integral part of implementation flows, PrimeTime continues to deliver the needed technology innovations and, at the same time, sets a new standard for performance and capacity to help keep up with Moore's law".

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