Product category:
Design and Development Software
News Release from: Synopsys | Subject: DFT Compiler and TetraMAX ATPG
Edited by the Electronicstalk Editorial
Team on 15 April 2004
Deep submicron designs stand the test of
time
The new releases of DFT Compiler and TetraMAX ATPG have improved design-for-test and automatic test pattern generation performance and pattern count for deep submicron designs.
The new releases of DFT Compiler and TetraMAX ATPG - key products in Synopsys' Galaxy Test Solution - have improved design-for-test (DFT) and automatic test pattern generation (ATPG) performance and pattern count for deep submicron (DSM) designs Customer benchmarks show two- to five-times improvement in DFT synthesis runtimes, and two- to three-times improvement in pattern count over the previous releases
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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This runtime improvement in Synopsys' DFT synthesis and ATPG products will help customers to significantly reduce overall test development time.
Furthermore, the improvement in TetraMAX ATPG pattern count will help customers to maintain and improve product quality for rapidly growing design sizes in 0.13-micron processes and below, while remaining within test cost constraints.
"Synopsys Galaxy Test solutions are part of our standard design flow today", said Masaaki Yoshida, Department Manager of Technology Foundation Development Division, NEC Electronics Corp.
"The new releases of DFT Compiler and TetraMAX provide two- to three-times faster runtime and three times more compact at-speed test vectors on our latest two-to-six-million gate designs".
DFT Compiler and TetraMAX (version 2003.12) deliver enhanced capabilities that further improve productivity and quality of results.
DFT Compiler's new rapid scan synthesis technology and new unified test DRC engine accelerate scan insertion and test design rule checking, enabling designers to complete design-for-test in significantly less time.
Improved TetraMAX ATPG algorithms help optimise compressed pattern generation for multimillion-gate designs, simultaneously improving performance while reducing pattern count.
"Fast, accurate test pattern generation that is capable of excellent coverage of the ARM cores is essential to our customers", said Tim Holden, EDA Relations Manager, ARM.
"Synopsys' newest version of TetraMAX enables us to reduce at-speed test pattern count by one half".
"Designers face the challenge of reducing their cost of test while improving product quality and meeting their time-to-market goals", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
"Our latest improvements in DFT Compiler and TetraMAX help customers achieve these goals and demonstrate our continued commitment to maintaining industry leadership in our Galaxy Test offerings".
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