Upgrade for silicon-versus-layout verification

Synopsys has made substantial enhancements to its SiVL silicon-versus-layout (SVL) verification tool - a key component of its design-for-manufacturing (DFM) solution.

Synopsys has made substantial enhancements to its SiVL silicon-versus-layout (SVL) verification tool - a key component of its design-for-manufacturing (DFM) solution.

SiVL compares a target design with its simulated silicon image in order to verify that the design is manufacturable.

Its proven silicon-correlated models, new "check-figure" capability and enhanced checking functionality ensure that key lithography induced errors are identified, all of which are essential for resolution enhancement technology (RET) closure.

RET closure is achieved when a design's layout matches its actual silicon image.

Accurate lithography simulation reduces the risk of respins, which can save hundreds of thousands of dollars in scrapped materials and months in production delays.

"As part of UMC's commitment to design for manufacturability (DFM), we continue to lead in the implementation of the most advanced lithography technologies", said Kuan Liao, Director of the CRD Advanced Module Division at UMC.

"This has helped us to minimise the potential for mask error at very deep submicron generations.

The SiVL verification tool is a welcome addition to our capabilities as we use it to support our 90 and 65 nanometre process technologies.

The excellent model accuracy coupled with the 'check-figure' capability helps us maintain accurate error coverage to avoid costly prototype delays caused by lithography errors".

Compared with 130nm designs, 65nm designs have up to 30 times more complex mask synthesis due to increased layout, model, and RET recipe complexity.

This increased complexity results in a proportional increase of the risk of lithography errors in mask and wafer fabrication.

Finding these lithography errors in order to achieve RET closure requires accurate, full-chip simulation and high error coverage.

To obtain accurate full-chip simulation, SiVL uses the production-proven, highly accurate, modelling technology from Synopsys' Proteus optical proximity correction (OPC) product.

SiVL's unique "check-figure" capability finds the critical features most likely to have errors before applying a combination of simulation-based lithography rule checks (LRC) to find real-world lithography errors.

It also uses and pattern based checks, such as mask rule checks (MRC), to improve mask manufacturability.

In order to achieve high error coverage, the checks are applied based on design style, feature-type and RET characteristics.

Accurate and thorough simulation based checking can be highly compute-intensive.

In order to meet the turnaround-time challenge, SiVL uses an intelligent, automated methodology to apply simulation only to the most error-prone areas, significantly reducing the simulation burden.

SiVL then distributes simulations using Synopsys' unique distributed processing capability that has been proven scalable in Synopsys' Proteus OPC tool when used on a computing platform containing over 1000 processors.

"The rapidly expanding use of RET in the 90 and 65 nanometre nodes dramatically increases the chances of killer lithography-related defects going undetected - which can easily result in weeks or months of product delay", stated Sandeep Khanna, Vice President of Marketing for Synopsys' Design For Manufacturing Group.

"With the new version of SiVL, Synopsys is delivering a verification solution to find these defects to obtain RET closure and prevent such costly time-to-market delays".

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