Product category:
Design and Development Software
News Release from: Synopsys | Subject: Galaxy
Edited by the Electronicstalk Editorial
Team on 10 June 2004
Reference flow takes design platform
onboard
The latest TSMC reference flow incorporates unique features and innovations of Synopsys' Galaxy design platform for designs at 130nm, 90nm and below.
The latest TSMC reference flow incorporates unique features and innovations of Synopsys' Galaxy design platform for designs at 130nm, 90nm and below Synopsys' Galaxy design platform addresses design challenges that include power management, power and signal integrity (SI), design for manufacturing (DFM) requirements for yield enhancement, testability, design planning and advanced flip chip capabilities in the TSMC Reference Flow Release 5.0
This article was originally published on Electronicstalk on 5 Feb 2003 at 8.00am (UK)
Related stories
Complete platform covers advanced IC design
The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools, to enable advanced IC design.
Test solution aids core-based design development
Synopsys has added a comprehensive test automation solution for core-based designs to its DFT Compiler, a key component of the Galaxy design platform.
This industry leading design methodology, based on the collaborative effort between both companies and a holistic approach to integrating semiconductor design and manufacturing, greatly reduces risk and shortens time to volume.
"Synopsys has made immense contributions to the TSMC Reference Flow since version 1.0.
We've worked collaboratively to ensure that Galaxy's unique power optimisation, testability, DFM handling for yield improvement, power integrity and advanced flip chip capabilities work seamlessly in our 5.0 Reference Flow", said Edward Wan, Senior Director of Design Services Marketing for TSMC.
Further reading
Analyser speeds to faster timing signoff
The latest release of PrimeTime - the timing backbone in Synopsys' Galaxy design platform - has set a new standard for performance in static timing analysis and signoff of multi-million-gate designs.
Tools form basis of TSMC Reference Flow
The Galaxy Design Platform and other Synopsys tools have been integrated into TSMC's advanced Reference Flow 4.0.
Design platform takes on signal integrity tool
Galaxy SI is a new and complete signal integrity solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration.
"Many of our customers haven't had to face these issues until recently".
"At 130 and 90 nanometres, power and manufacturing concerns are becoming as important as timing and signal integrity".
"The Galaxy Design Platform addresses these issues".
"Our customers tell us they need tools and flows that address the special requirements of 90 nanometre and below designs", said John Chilton, Senior Vice President and General Manager of Synopsys' Solutions Group.
"We've worked closely with TSMC, to help ensure that our industry-standard Galaxy design platform, DFM family of products, and DesignWare IP, including process-tuned TSMC libraries, offer the solutions that designers need to face these challenges".
"We look forward to a continued collaboration with TSMC on the critical design development steps - from RTL to silicon - as we probe even deeper into the 90 nanometre and below design challenges".
The TSMC Reference Flow 5.0 specifically targets power closure.
Synopsys' low power solution offers dynamic power management optimisations in standby and shutdown mode, leakage power reduction using TSMC's multi-threshold libraries, and static IR analysis in the flow.
At 90nm and below, yield is a big concern.
Synopsys and TSMC also worked together to ensure manufacturing issues are considered at the beginning of the design phase to improve yield.
Synopsys' Astro physical optimisation, placement and routing solution is now enhanced to allow timing-driven metal fill, wire spreading and via engineering change order (ECO) capabilities to address important DFM requirements.
In addition, the advanced flip chip flow is designed to handle ultra high pin count designs that are common for 90nm and below designs.
These capabilities join previously established Synopsys solutions in the TSMC flow for timing and SI closure.
Synopsys' JupiterXT design planning solution has been adopted by TSMC in Reference Flow 5.0 to provide automatic macro placement and pin assignment capabilities.
This enables faster runtime to create a detailed floorplan.
In addition, TSMC has also implemented deterministic logic BIST (DBIST) technology using Synopsys' DFT Compiler SoCBIST solution, thus significantly reducing both test data volume and test application time without compromising fault coverage.
Synopsys' PrimeTime SI is also included in Reference Flow 5.0 for crosstalk delay, noise (glitch) and IR drop delay analysis.
The Galaxy Design Platform is a key component of TSMC's reference flow 5.0.
The flow includes Astro, Astro-Rail, Astro-Xtalk, Design Compiler, DFT Compiler, Hercules PVS, Jupiter-XT, Physical Compiler, Power Compiler, Star-RCXT, PrimePower, PrimeTime, PrimeTime SI, and TetraMAX.
From the Discovery Verification Platform, VCS and HSpice are also part of the flow.
Synopsys' DesignWare Library, the most widely used silicon intellectual property (IP) collection, is also an integral part of the Reference Flow.
Synopsys Professional Services offers chip implementation and flow deployment with TSMC Reference Flow.
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
