Renesas standardises on signoff solution
Renesas Technology Corp has standardised on Synopsys' Star-RCXT for resistive-capacitive (RC) parasitic extraction in its design flow.
Renesas Technology Corp has standardised on Synopsys' Star-RCXT for resistive-capacitive (RC) parasitic extraction in its design flow.
With Synopsys' Star-RCXT in its Galaxy Design flow, Renesas Technology now has a complete signoff solution that accelerates timing and signal integrity (SI) closure for their 130 and 90nm designs.
"Using Synopsys' Star-RCXT for accurate RC parasitic extraction with PrimeTime for static timing analysis, we successfully taped out several multi-million-gate chips", said Hisaharu Miwa, Department Manager, EDA Technology Development Department, Design Technology Division, LSI Product Technology Unit, Renesas Technology Corp.
"Based on these results, we have standardised on Star-RCXT for parasitic extraction in our signoff flow for 90 nanometre designs".
Star-RCXT is the market-leading parasitic extraction solution, offering the highest performance, capacity and accuracy for cell-based, custom digital and analogue/mixed signal designs.
Star-RCXT supports key 90nm process capabilities including in-die process variation solutions - such as selective process biasing (spacing and width dependent metal bias), local density effects (LDE), length of diffusion (LOD) - and metal fill.
In modelling such advanced silicon process features, Star-RCXT extracts highly accurate RC parasitics for PrimeTime SI to ensure concurrent timing and signal integrity signoff.
"Synopsys Star-RCXT and PrimeTime are the standard for silicon correlation and signoff in eight out of the ten leading semiconductor design flows today", said Antun Domic, Senior Vice President and General Manager of Synopsys' Implementation Group.
"By standardising on Synopsys' proven signoff solution within their Galaxy Design flow, Renesas Technology is now able to deliver its next-generation products to market with first-pass silicon success".
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