Platform helps meet wireless SoC yield goals

Renesas Technology Corp has taped out a 90nm SoC design for wireless applications using Synopsys' Galaxy Design Platform.

Renesas Technology Corp has taped out a 90nm system-on-chip (SoC) design for wireless applications using Synopsys' Galaxy Design Platform.

Synopsys' physical design solution - with advanced design for yield (DFY) capabilities in the Astro product - enabled Renesas Technology to meet its yield goals in this 90nm production design.

"With this being our 90-nanometre wireless design, we were concerned about DFM issues", said Teruaki Harada, Department Manager of DFM and EDA Technology Development Dept, Design Technology Division, Renesas Technology Corp.

"The yield enhancement techniques in Synopsys' Galaxy Design Platform, particularly the Astro product's ability to insert redundant vias and efficiently enforce antenna rules, helped us significantly optimise our design and achieve our 90nm yield targets".

The Renesas Technology multi-million-gate design was created using Synopsys' physical design solution - the Design Compiler product for synthesis, the Power Compiler product for dynamic and leakage power optimisation, the Physical Compiler and Astro products for physical implementation, and the Star-RCXT product for full-chip parasitic extraction.

The yield-aware routing optimisation techniques in the Astro product - such as redundant via insertion - helped Renesas Technology minimise impact on timing-critical nets and optimise for yield while maintaining a predictable convergence to timing closure.

"Synopsys is working closely with semiconductor vendors to deliver comprehensive yield-enhancement strategies", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.

"Companies such as Renesas Technology turn to Synopsys as their vendor of choice for physical design when they need advanced design for yield techniques to meet their yield goals and deliver cost-effective chips on time".

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