Product category:
Design and Development Software
News Release from: Synopsys | Subject: VCS' SystemVerilog
Edited by the Electronicstalk Editorial
Team on 02 November 2005
Simulator helps Exar speed up chip
development
Synopsys has announced that Exar has adopted its VCS comprehensive RTL verification, a key component of the Discovery Verification Platform, to speed chip development.
Synopsys has announced that Exar has adopted its VCS comprehensive RTL verification, a key component of the Discovery Verification Platform, to speed chip development and increase verification quality Exar has taken advantage of VCS' SystemVerilog test bench automation capabilities to rapidly develop an advanced, extensible verification environment based on open standards, leveraging the latest coverage-driven, constrained-random methodologies
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Exar used these methodologies with the VCS solution to identify bugs early in the design process where they were easily corrected.
"After evaluating other tools, we chose VCS because of its leading support for verification with SystemVerilog and the high performance of its native test bench technology", said Sameer Goyal, Principal Engineer at Exar.
"With the VCS solution, we developed a sophisticated coverage-driven, constrained-random verification environment using SystemVerilog with just four months of effort".
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"This helped us shorten the development cycle down to one third compared with previous projects".
Exar engineers developed a sophisticated SystemVerilog verification environment, using the VCS solution to simulate a complex design, generate randomised stimulus and measure functional coverage.
The Exar team was able to quickly learn the SystemVerilog language and create an advanced test bench, which enabled full randomisation of many aspects of the environment, from port configuration to characteristics of the packet and its subfields.
They also developed a high-level reference model for checking correct design behaviour, taking advantage of the VCS solution's support of advanced SystemVerilog language features, including object-oriented programming, classes, functional coverage, arrays, mailboxes and semaphores.
Exar was able to quickly find unanticipated corner-case bugs in both the design and reference model by using the VCS solution's powerful constrained-random stimulus generation to create thousands of realistic tests.
"The VCS solution's support for SystemVerilog verification features enables customers like Exar to quickly build and deploy advanced test benches based on open standards", said Manoj Gandhi, Senior Vice President and General Manager, Verification Group at Synopsys.
"VCS single-compiler technology for design, testbench, assertions and coverage provides higher performance, enabling our customers to verify designs in less time and with higher confidence".
The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed-signal, system-level verification, assertions, DesignWare verification intellectual property, code coverage, functional coverage, test benches and formal analysis.
Combined with support for industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemC and OpenVera, and Synopsys' proven Reference Verification Methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.
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