Product category:
Design and Development Software
News Release from: Synopsys | Subject: DFT MAX's Adaptive Scan technology
Edited by the Electronicstalk Editorial
Team on 08 November 2005
Adaptive scan technology reduces tester
costs
Genesis Microchip, supplier of display image ICs, has successfully deployed DFT MAX adaptive scan technology to reduce tester costs.
Genesis Microchip, supplier of display image ICs, has successfully deployed DFT MAX to reduce tester costs DFT MAX's adaptive scan technology enables scan compression that reduces both test application time and test data volume by up to 50 times over traditional scan techniques
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Genesis designers achieved 90% test data volume reduction on a recent design for a flat panel display controller which led to their decision to adopt DFT MAX within the Galaxy(TX) Design Platform solution.
"We have seen measurable test cost reduction with Synopsys' DFT MAX - from RTL synthesis through physical implementation - and are very satisfied", said T.
Chan, Senior Vice President of Product Development, Genesis Microchip.
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"DFT MAX's adaptive scan technology is a straightforward extension to traditional scan currently being implemented at Genesis using Synopsys' DFT Compiler, Physical Compiler and TetraMAX ATPG design flows".
"Tester time reduction, along with low area impact on the design, are the main driving forces leading to our adoption of DFT MAX".
Packaging requirements limited the number of pins available for testing Genesis' controller IC.
These limitations could have led to a substantial increase in the amount of test data required per pin along with an increase in tester costs associated with managing the larger data volume.
Genesis designers used DFT MAX with the Galaxy Design product family to substantially reduce the number of test patterns, thereby meeting both their packaging constraints and their test coverage needs.
To Genesis' satisfaction, when the device was fabricated, the ATPG test patterns passed on the tester within hours.
"There is a growing need to reduce both test data volume and test application time to lower tester costs as well as make room in memory for the additional tests needed to detect deep sub-micron defects", said Graham Etchells, Director of Marketing, Synopsys Test Automation Business Unit.
"What has been missing in the industry is a solution that is as easy to implement as scan, and works concurrently with downstream physical design flows".
"With DFT MAX we have achieved that goal and, given all the successes our customers are having with it, we believe DFT MAX will become the de facto standard for scan compression".
DFT MAX Adaptive Scan uses advanced scan compression technology to minimise tester costs by reducing both test application time and test data volume by up to 50 times, compared with traditional scan techniques.
DFT MAX's key advantage is that it is easy to implement and is less intrusive on design flows and design performance than alternative methods.
Fragmented bolt-on flows requiring separate design synthesis and test compression insertion steps can break critical timing, add routing congestion and necessitate subsequent re-optimisation.
DFT MAX by contrast is integrated with the Galaxy physical design flow to eliminate costly, time-consuming design iterations between synthesis and physical implementation.
Simultaneously, designers achieve convergence of timing, power, area and test.
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