Design flow speeds switch to 90nm process

A 90nm reference design flow optimised for low-power SoC designs is based on Synopsys' Galaxy Design Platform, ARM Artisan Sage-X standard cell library and UMC's 90nm process.

Synopsys has developed a 90nm reference design flow optimised for low-power system-on-chip (SoC) designs.

The validated RTL-to-GDSII design flow is based on Synopsys' Galaxy Design Platform, ARM Artisan Sage-X standard cell library and UMC's 90nm process.

It addresses leakage power challenges at 90nm and provides advanced design-for-manufacturing (DFM) capabilities for faster yield ramp and lower development costs.

"At UMC, we recognise the importance of working with leading EDA companies such as Synopsys to deliver silicon-validated reference design flows that address the SoC design challenges encountered at nanometre technologies", said Ken Liou, Director of the IP and Design Support Division at UMC.

"This latest development with Synopsys is specifically designed to give customers the benefit of both companies' expertise to help them achieve first pass silicon success with reduced time and risk".

The reference design flow incorporates many of Synopsys' Galaxy Design Platform's low power and design-for-manufacturing innovations, including Power Network Synthesis (PNS) and Power Network Analysis (PNA) products, which are used to design power plans at the floorplanning stage.

Other floorplanning capabilities include virtual flat floorplanning with physical hierarchy-aware global routing, virtual timing optimisation, and macro placement with automatic hierarchy detection.

Designers can create an optimised initial design floor plan using these advanced features to guide them to the next design steps in physical synthesis and place and route.

By following this plan, designers can achieve faster timing closure and avoid design iterations.

The reference design flow also features multithreshold (MVth) optimisation to take advantage of the available UMC 90nm multithreshold libraries for leakage power reduction.

In addition, the flow supports advanced signal integrity capabilities to perform analyses for electro migration (EM) and voltage drop (IR) that are crucial in avoiding design failure in 90nm and below designs.

"Our close relationship with UMC helps ensure that the reference flow will satisfy the demands of even the most advanced designers dealing with 90-nanometre process design issues in power optimisation and design for manufacturing and yield", said Rich Goldman, Vice President of Strategic Market Development at Synopsys.

"This collaboration builds on UMC's advanced technology and Synopsys' Professional Services proven expertise to give designers access to an optimised path to silicon that delivers higher quality of results while speeding time to results".

Synopsys has brought several new DFM capabilities to the new 90nm reference design flow.

One example is the addition of timing-driven dummy metal insertion to specifically meet UMC's metal density requirements while maintaining timing closure, and automatic redundant via and via farm insertion.

These new DFM capabilities can help designers improve reliability and are supported in Synopsys' place-and-route solution.

The UMC/Synopsys reference design flow is available now.

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