Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 27 January 2006
Japanese companies add support for
SystemVerilog
The Verification Methodology Manual for SystemVerilog has been endorsed by the Semiconductor Technology Academic Research Centre and major electronics companies in Japan.
The Verification Methodology Manual (VMM) for SystemVerilog has been endorsed by the Semiconductor Technology Academic Research Centre (STARC) and major electronics companies in Japan as a reference to develop advanced verification environments based on the IEEE standard SystemVerilog language The Japanese-language edition of the manual will be published by CQ Publishing in Japan
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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More than 1800 copies of the English-language edition have been sold to date.
The manual, co-authored by verification experts from ARM and Synopsys, describes how to use SystemVerilog to create comprehensive verification environments using coverage-driven, constrained-random and assertion-based techniques, and specifies library building blocks for interoperable verification components.
The VMM for SystemVerilog, reviewed by verification engineers from more than 30 semiconductor industry companies, helps enable chip development teams to achieve measurable functional coverage goals in less time with less effort, giving verification engineers and managers the confidence to tape out complex system-on-chip (SoC) and silicon intellectual property (IP) designs.
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"The VMM for SystemVerilog is our recommended reference book to architect SystemVerilog verification environments", said Yoshiharu Furui, Senior Manager, IP Reuse Engineering Group at STARC Japan.
"It defines the state-of-the-art for advanced, coverage-driven functional verification that engineers can use to increase chip development productivity and quality, and will complement the IP Functional Verification Guide being developed by the STARC IP Reuse Engineering Group".
"The VMM for SystemVerilog has been quickly established as an industry-leading reference for advanced verification with SystemVerilog", said Takafumi Nishijima, president, ARM KK.
"We welcome STARC's endorsement of this manual and the availability of a Japanese-language edition".
"Companies around the world are adopting SystemVerilog and taking advantage of the advanced methodologies enabled by the language", said Kimio Fujii, President of Nihon Synopsys, the company's Japanese subsidiary.
"Just as the Reuse Methodology Manual (RMM) for system-on-a-chip designs established the open, industry standard for design reuse and reusable silicon IP, the Verification Methodology Manual for SystemVerilog defines an open, industry standard for advanced verification and interoperable verification IP with SystemVerilog".
"The VMM for SystemVerilog will enable all SoC and IP projects to establish an effective, predictable and reusable verification process using SystemVerilog that is based on the experience of leading industry experts", said Yoshio Takamine, Group Manager, System Level Design and Verification Technology Development, Renesas Technology Corp.
"The VMM for SystemVerilog will enable any SoC or IP development team to achieve higher levels of verification productivity and quality by providing a standard, interoperable methodology for taking advantage of the coverage-driven, constrained-random techniques used by industry experts", said Zenji Oka, Manager Electronic Devices Company, Ricoh Company.
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