IEC award for testbench automation tool

The Pioneer-NTB SystemVerilog testbench automation tool has been honoured as the recipient in the design verification category in the annual IEC DesignVision Awards.

The Pioneer-NTB SystemVerilog testbench automation tool, a component of Synopsys' Discovery Verification Platform, has been honoured as the recipient in the design verification category in the annual International Engineering Consortium (IEC) DesignVision Awards programme.

This is the second year in a row that Synopsys has been recognised for its innovation and leadership in verification.

An industry panel, sponsored by the IEC, selected the Pioneer-NTB tool based on multiple criteria, including innovation, uniqueness, market impact and customer benefits.

Pioneer-NTB enables verification teams to deploy Synopsys' advanced verification methodologies built on open industry standards in a VHDL, Verilog or mixed-language environment to find more bugs faster with increased productivity.

"The DesignVision Awards recognise innovative products and services that support the work of electronic design engineers, the core audience at DesignCon", said Barry Sullivan, DesignCon 2006 Programme Director.

"The IEC is pleased to provide this recognition to companies whose products exemplify our standard of service to the industry".

The Pioneer-NTB SystemVerilog testbench automation tool increases verification productivity and improves the quality of complex SoC and IP designs by enabling engineers to use advanced coverage-driven, constrained-random and assertion-based verification techniques.

It allows engineers to take advantage of these proven verification technologies on third-party VHDL and Verilog simulators.

The tool provides easy-to-use connections from its SystemVerilog verification environment to popular third-party simulators.

By using Pioneer-NTB, verification engineers can adopt a single, standards-based, advanced verification infrastructure in mixed-simulation environments.

The Pioneer-NTB tool is built on Synopsys' proven VCS and Vera technology and takes advantage of the extensive ecosystems built around the solutions, including methodology, debug and analysis environments, assertion IP and verification IP.

The tool fully supports the Verification Methodology Manual for SystemVerilog, enabling chip development teams to adopt the same best practices used by experts, resulting in more efficient and more thorough verification.

"As the industry leader in SystemVerilog design and verification, we are honoured to see Synopsys' SystemVerilog testbench automation technology chosen for a DesignVision Award by the IEC", said George Zafiropoulos, Vice President of Marketing, Synopsys Verification Group.

"Pioneer-NTB demonstrates Synopsys' commitment to delivering industry leading SystemVerilog-based solutions to the market and provides users an efficient path away from proprietary legacy verification environments towards an industry standard SystemVerilog environment".

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