Design for test saves wireless IC costs

Wireless IC specialist CSR has successfully used Synopsys' DFT MAX to reduce digital tester costs.

Wireless IC specialist CSR has successfully used Synopsys' DFT MAX to reduce digital tester costs.

CSR needed a design-for-test solution that would meet its high quality goals, yet would be easy to implement and have minimal silicon area overhead.

DFT MAX was deployed as part of the Synopsys Galaxy Design Platform and achieved 90% digital test time/test data reduction for several BlueCore designs.

When the devices were fabricated, the test patterns were applied successfully to validate the silicon.

"We needed very high quality levels for our high-volume manufactured designs to minimise the number of field escapes", said James Collier, Chief Technical Officer and cofounder of CSR.

"At the same time, we wanted to avoid a corresponding increase in tester costs, if possible".

"Using DFT MAX to reduce digital test data volume by 90%, we were able to add DSM testing to our test suite to further increase quality without the need for expensive tester hardware upgrades".

"Moreover, reduction in test execution time achieved by DFT MAX actually decreased our overall tester costs".

CSR designers were also pleased to discover how easy it is to implement DFT MAX for scan compression.

"Our team was optimistic about the cost benefits of using DFT MAX but anticipated it would take a while to learn how to adopt it for production use", said Alan Duffy, CSR Design Engineer.

"However, we got it working the first day just by adding a couple of lines to our synthesis scripts".

"It is unlikely we will undertake any more designs without using DFT MAX for scan compression".

Working seamlessly as part of the Galaxy Design Platform, DFT MAX predictably reduces test costs by up to 50x compared with traditional scan techniques.

The key advantage of DFT MAX is that it is easy to implement and is far less intrusive on design flows and design performance than alternative solutions.

The Galaxy platform delivers design engineers a single environment for synthesis, physical implementation and signoff.

Concurrent optimisation for timing, signal integrity, area, power and test within the Galaxy environment helps eliminate costly and time-consuming design iterations between front-end and back-end flows.

"Designers are under immense competitive pressure to deliver high-quality parts at lower cost than ever before", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.

"Simultaneously, designers must realise their quality and cost goals in shorter timeframes".

"To obtain predictable results quickly, the Galaxy Design Platform considers all the critical timing, signal integrity, area and power effects of adding test logic to a design".

"DFT MAX helped CSR achieve its test goals in record time".

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