Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 05 May 2006
Irish consultants support methodology
manual
Silicon and Software Systems is supporting the Synopsys VCS comprehensive RTL verification solution and the verification methodology manual for SystemVerilog.
Dublin-based Silicon and Software Systems (S3), a leading provider of design and consulting services for integrated circuits and embedded software, is supporting the Synopsys VCS comprehensive RTL verification solution and the verification methodology manual (VMM) for SystemVerilog S3 will use the VCS solution and the VMM for SystemVerilog to develop products for a wide variety of wireless, consumer, and network systems applications
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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S3 is deploying SystemVerilog because it is the first and only nonproprietary language with broad industry support to enable an advanced verification methodology.
The VMM for SystemVerilog gives S3 access to an open, proven methodology with a well-defined structure.
The Synopsys VCS solution provides S3 with the best support for SystemVerilog through Native Testbench (NTB) technology, as well as for designs written in VHDL.
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These silicon-proven capabilities will reduce risk and enable predictable success for S3's designs across a wide range of applications.
"We support SystemVerilog and the VMM for SystemVerilog because nonproprietary verification solutions give us the flexibility we need to verify our broad range of system and silicon designs", said Dermot Barry, General Manager, System IC Business Unit at S3.
"The VCS verification solution and the Native Testbench technology for SystemVerilog, along with the proven verification concepts detailed in the VMM for SystemVerilog, are a powerful combination that gives us a high-performance, low-risk solution for our leading-edge silicon products".
SystemVerilog is a major extension of the established Verilog language that dramatically improves productivity in the development of large-gate-count, intellectual property-based, bus-intensive chips.
SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow.
"S3 adopted SystemVerilog and the VMM for SystemVerilog because they provide a stable, open-standard language and methodology to address S3's verification challenges for both VHDL and Verilog designs", said George Zafiropoulos, Vice President of Marketing, Verification Group at Synopsys.
"Because the VCS solution provides high performance through its Native Testbench technology and full support for the VMM for SystemVerilog, it has become the preferred solution for advanced verification using the standard language".
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