Product category:
Design and Development Software
News Release from: Synopsys | Subject: IC Compiler
Edited by the Electronicstalk Editorial
Team on 30 June 2006
Synopsys continues IC Compiler momentum
Synopsys has announced the 2006.06 release of IC Compiler, Synopsys' next-generation place-and-router
Synopsys has announced the 2006.06 release of IC Compiler, Synopsys' next-generation place-and-router The 2006.06 release delivers advances in the areas of integrated design planning, enhanced physical test, advanced low-power design, true concurrent multi-corner/multi-mode optimisation, and design-for-yield techniques
This article was originally published on Electronicstalk on 20 Feb 2006 at 8.00am (UK)
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"IC Compiler has seen strong support among our key customers who have a diverse family of designs and are often at the leading edge in adopting new technology," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group.
"Synopsys holds leading technology positions in physical design, optimisation, sign-off and design-for-manufacturing (DFM), and we are bringing these technologies together to make IC design more efficient".
"The 2006.06 release is yet another example of continued technology delivery and further distances IC Compiler from the field." The 2006.06 release allows flat floorplan creation and refinement in the same environment as physical implementation - placement, clock tree, and routing.
These capabilities utilize proven technologies from the JupiterXT tool for floorplanning, automatic high-quality macro placement, and automatic power-network synthesis and analysis.
The integration brings about commonality in graphical user-interface, timing analysis, placement, and global routing technologies, to drive higher-quality floorplanning and faster time to results.
The 2006.06 release also includes enhanced capabilities for low-power design, manufacturing testability and design-for-yield (DFY).
It provides improvements in multi-Vt leakage power optimizations as well as advanced leakage management with MTCMOS power-gating.
The release introduces a new syntax for capturing power-domain specifications and enhances Synopsys' Liberty library format for MTCMOS power modeling.
Also included is the SCANDEF-based interface to RTL-based scan synthesis using DFT MAX, and integrated support for scan-chain repartitioning and reordering to reduce congestion and improve routability.
In the area of DFM, the 2006.06 release adds to the existing set of capabilities for impacting yield during design, including intelligent multi-pattern via optimisation, timing-driven wire spreading, timing-driven metal fill, and critical area analysis.
New capabilities include timing-driven via redundancy, staggered metal fill, and timing-driven half-pitch wire spreading after detail route.
Another key new capability in limited customer availability is lithography hot-spot fixing.
Today, many advanced designs need to operate in several different functional modes.
In addition, deep-submicron geometries require designs to be characterized across multiple process corners.
A key requirement arising from these factors is the ability to concurrently optimise across multiple modes and corners.
The 2006.06 release of IC Compiler brings this capability into general availability.
In addition, the release provides early support for signoff-driven closure for advanced designs, bringing in exact sign-off data from incremental runs of the PrimeTime static timing analysis and Star-RCXT extraction tools.
Used together, true concurrent multi-mode/multi-corner optimisation and sign-off driven closure provide a big boost in designer productivity for advanced designs.
The IC Compiler 2006.06 release is available immediately.
IC Compiler is Synopsys' next-generation place-and-route system.
It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure.
Current-generation solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations.
IC Compiler's Extended Physical Synthesis (XPS) technology breaks down the walls between these steps by extending physical synthesis to full place-and-route.
IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of the best Synopsys core technologies.
It is a complete place-and-route system with everything necessary to implement next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimisation, power reduction, design-for-test (DFT), and yield optimisation.
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