Product category:
Design and Development Software
News Release from: Synopsys | Subject: Advanced HDTV chip
Edited by the Electronicstalk Editorial
Team on 30 June 2006
HDTV chip with Synopsys' IC Compiler
taped out
Synopsys has announced that Micronas has taped out one of its advanced HDTV (high-definition television) chips using Synopsys' IC Compiler.
Synopsys has announced that Micronas has taped out one of its advanced HDTV (high-definition television) chips using Synopsys' IC Compiler This new chip is a key part of Micronas' drive to improve picture and sound quality for flat-panel TV and to provide benefits to manufacturers in the total cost structure from RandD to production, based on very high integration
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The price-performance pressures associated with this intensely competitive market put extreme requirements on chip design, requiring the highest silicon utilization (i.e., smallest possible die size) without compromising processing performance.
Using the Galaxy design platform with new IC Compiler optimisation technology, Micronas was able to tape out this design at the required performance while achieving a remarkably high utilization in excess of 90 percent.
"IC Compiler's highly efficient optimisation technology was critical in helping us achieve our objectives for die-size and component cost," said Dirk Wieberneit, vice president, Product Development, Consumer at Micronas.
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"We have decided to standardize on the Galaxy platform for all our design work because we've found that its close integration of tools, algorithms, and libraries has increased the efficiency of our teams and helped to lower our overall cost of design." The IC Compiler solution's unique Extended Physical Synthesis (XPS) technology was a major factor in enabling Micronas to achieve both the performance and cost goals of this project.
XPS is the architecture that increases IC Compiler efficiency by combining synthesis, placement, clock and routing in a unified optimisation environment.
Another element used by Micronas to reduce the die size was IC Compiler's new congestion-reduction algorithm that automatically resolves local congestion hot-spots and increases the maximum achievable utilization.
Micronas also applied Synopsys' design-for-test (DFT) solution successfully for maximum efficiency.
The DFT MAX tool was used to automatically implement test compression that can reduce testing costs by up to 50X with minimal area overhead.
This design also benefited from IC Compiler's physical test optimisation techniques, including scan chain repartitioning and reordering for reduced congestion.
"Micronas has been a major strategic customer for Synopsys and was an early adopter of our new technologies, including DFT MAX and IC Compiler," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group.
"This tapeout and the impressive overall results are a strong endorsement of the depth of Synopsys technology and Micronas' design expertise.".
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