Product category:
Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare Mixed-Signal connectivity
Edited by the Electronicstalk Editorial
Team on 13 July 2006
IBM and Chartered team with Synopsys
Synopsys USB, PCIe, SATA and XAUI PHYs for high-volume, low-power applications available for foundries' leading-edge processes
Synopsys, a world leader in semiconductor design software, has announced that IBM and Chartered Semiconductor Manufacturing have agreed to support Synopsys' DesignWare Mixed-Signal connectivity intellectual property (IP) on the 65 nm process developed for Common Platform technology As part of this agreement, Synopsys is porting PHYs for USB 2.0, PCI Express (PCIe), SATA and XAUI protocols to the 65 nm process technology developed by Chartered, IBM, Infineon Technologies and Samsung, and also porting the DesignWare USB 2.0 nanoPHY IP to IBM and Chartered's 90 nm process node
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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These PHYs are highly complex process-tuned analogue interfaces used in today's high-volume, high-value consumer, computer, storage and networking applications.
Availability of this DesignWare PHY IP will give designers access to verified connectivity cores for implementation at 65 nm to help reduce risk, speed time-to-market and ensure a more predictable path to silicon.
Introduced earlier this year, the DesignWare USB 2.0 nanoPHY IP features half the power and die area compared to previous generation solutions.
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The 90 nm IP silicon has received Hi-Speed USB logo-certification and the 65 nm version is in final development.
Synopsys is porting DesignWare PHYs for the popular PCIe, SATA and XAUI protocols to the 65 nm process node to give designer's access to standards-compliant IP with high-value features, such as low power and small area.
"High speed connectivity IP is a critical building block in many of today's leading edge designs".
"We selected Synopsys because of their expertise in complex mixed-signal connectivity IP and ability to deliver IP in the context of a complete solution", said Steven Longoria, vice president, Semiconductor Technology Platform at IBM Technology Collaborations Solutions.
"We are focused on continually expanding the Common Platform technology ecosystem with validated process-aware IP".
"These PHYs will be available to both our ASIC and foundry clients".
"Our customers require that the Common Platform offers early availability of standardised interface IP for USB, PCIe, SATA and XAUI protocols that can be manufactured with confidence at multiple foundries", said Kevin Meyer, vice president of Worldwide Marketing and Platform Alliances at Chartered.
"These high-value cores from Synopsys allow chip designers to quickly obtain and integrate critical functionality into their designs and then ramp into volume production at Chartered or IBM".
"We are taking an even more aggressive position in making available reduced-risk IP at the leading edge, being among the first companies at 65 nm to have Synopsys port this IP".
"Availability of reliable mixed-signal IP has become central to enable the migration of SoC designs to smaller geometries", said Guri Stark, vice president of Marketing for the Solutions Group at Synopsys.
"We've worked closely with IBM and Chartered to deliver these key IP cores to help designers achieve power and area savings in 65-nm and 90-nm chip designs".
"Combining these PHYs with our other IP offerings and a complete Common Platform technology reference design flow make Synopsys the obvious choice for designers who want to take advantage of the flexibility, reduced risk and cost savings of the Common Platform technology".
Synopsys' DesignWare USB 2.0 nanoPHY IP is available now for the CMOS 9SF and CMOS 9LP 90 nm processes and in Q3'06 for the CMOS 10LP 65-nm process.
PCI Express, SATA and XAUI PHYs are expected be available in Q4 of calendar 2006 for the CMOS 10LP 65 nm process.
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