Platforms support 65nm reference flow

Synopsys' Galaxy design and DFM platforms support TSMC's Reference Flow 7.0.

Synopsys' Galaxy design and DFM platforms support TSMC's Reference Flow 7.0.

The Reference Flow 7.0 includes Synopsys' IC Compiler next-generation physical implementation to provide new low-power and yield capabilities that address 65-nanometre design challenges.

This collaborative effort between the two companies brings together advanced semiconductor design and manufacturing to achieve optimum IC performance, power, and yield with higher predictability.

TSMC's Reference Flow 7.0 uses key capabilities of Synopsys' Galaxy design platform to address low-power and yield requirements, including: concurrent multicorner/multimode optimisation for multivoltage designs; and chemical mechanical polishing (CMP)-aware model-based metal fill for optimal results in metal thickness.

"As customers move their designs into 65-nanometre processes, power management and design for manufacturing become as important as traditional timing and signal integrity challenges", said Ed Wan, senior director of design service marketing at TSMC.

"Synopsys' newest design and manufacturing capabilities address the key requirements of TSMC's Reference Flow 7.0 to maximise the benefits of our advanced technology for 65-nanometre design".

"TSMC and Synopsys continually evaluate and address the needs of our designers with enhancements to the reference flow", said John Chilton, senior vice president and general manager of Synopsys' Solutions Group.

"Our ongoing collaborative efforts help ensure that Synopsys' low power-optimisation, statistical analysis and advanced yield technologies provide optimum silicon performance with high predictability".

The TSMC Reference Flow 7.0 includes new low-power design capabilities within Synopsys' Galaxy design platform, including power domain specification and verification at the RTL level, concurrent multicorner/multimode optimisation for multivoltage designs, coarse-grain multithreshold CMOS (MTCMOS) logic for leakage mitigation, and dynamic voltage-drop analysis considering MTCMOS rush currents.

Synopsys' existing production-proven low-power design methodologies such as clock gating, power network synthesis, power-aware placement, low-power clock-tree synthesis, multithreshold leakage power optimisation, and static/dynamic voltage-drop analysis are also included in the Reference Flow 7.0.

Reference Flow 7.0 includes new capabilities that enhance yield during design, including implementation support for 65-nanometre design rules, Critical Area Analysis (CAA), and CMP simulation and metal fill.

Reference Flow 7.0 incorporates a complete Synopsys-based RTL-to-GDSII solution utilising the Galaxy Design Platform for RTL synthesis, physical implementation and sign-off, and the Discovery Verification Platform with VCS and HSPICE for RTL verification and circuit simulation.

As an integral part of the reference flow, extensive Galaxy support includes Design Compiler logic synthesis solution, Power Compiler multivoltage power management solution, Leda RTL Checker, DFT MAX 1-pass test synthesis solution, Jupiter-XT physical planning solution, IC Compiler physical implementation solutions, PrimeTime and PrimeTime SI static timing and signal integrity sign-off solutions, PrimeRail power network sign-off solution, PrimePower and PrimeTime PX full-chip power analysis solution, Star-RCXT extraction solution, Hercules PVS physical verification solution, and TetraMAX automatic test generation (ATPG) solution.

In addition, Synopsys Professional Services provides expertise in chip implementation and flow deployment services with Reference Flow 7.0.

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