Product category:
Design and Development Software
News Release from: Synopsys | Subject: Primeyield LCC
Edited by the Electronicstalk Editorial
Team on 26 July 2006
Synopsys primeyield LCC links to IC
compiler
Synopsys primeyield LCC links to IC compiler for automated correction of lithography problems
Synopsys has announced that PrimeYield-the company's new, comprehensive tool suite for design-yield analysis-enables automated correction of manufacturing problems early in the design process Announced today PrimeYield integrates design with manufacturing by accurately predicting design-induced mechanisms that threaten yield and by providing automated correction guidance to upstream design implementation tools
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
Related stories
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
Tensilica standardises on Physical Compiler
Tensilica has standardised on Synopsys Physical Compiler and developed a high-performance reference flow around Physical Compiler for its Xtensa V processor cores.
The lithography compliance-checking (LCC) module within PrimeYield tightly links to Synopsys' IC Compiler advanced physical implementation solution, enabling fast detection and correction of litho-related issues for 65nm and smaller chip designs.
"Design-team productivity is imperative to us," said Yukihito Oowaki, Senior Manager System LSI Design Dept., Toshiba Corporation Semiconductor Company.
"Synopsys' PrimeYield LCC provides an automatic and seamless method for us to detect lithography problems and deliver correction guidance to our place-and-route environment, IC Compiler".
Further reading
PCI core gets official seal of approval
In conjunction with IP 2001 Japan, Synopsys has announced the PCI Special Interest Group (PCI-SIG) certification of the DesignWare PCI-X MacroCell.
Power Compiler adds pushbutton power optimisation
Oki Semiconductor has added Power Compiler, Synopsys' pushbutton power optimisation tool for RTL and gate-level designs, to the set of Synopsys tools offered in Oki's advanced ASIC design kit.
"We are very excited about the efficiency and accuracy of Synopsys' PrimeYield LCC technology and will be deploying it into our standard layout flow".
PrimeYield gives designers a preview of the issues that will impact the manufacturability of their devices at 65nm and below advanced technology nodes.
PrimeYield addresses these issues via its three core modules-LCC; model-based chemical-mechanical polishing (CMP) checking; and critical area analysis (CAA)-providing designers with the critical toolset they need to correct and modify the design before tapeout.
PrimeYield's tight links to design implementation enable it to drive automatic correction within IC Compiler and accurate parasitic extraction within the Star-RCXT tool.
Variation-aware extensions of Synopsys' gold-standard PrimeTime static timing analysis and Star-RCXT extraction tools were also announced today, further strengthening the link between design and manufacturing to help customers improve design robustness and parametric yield at 65nm and below.
IC Compiler is an advanced physical implementation solution with everything necessary to do next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimisation, power reduction, design-for-test (DFT), and yield optimisation.
IC Compiler provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure.
"With the introduction of PrimeYield, Synopsys delivers an automated solution that both identifies and fixes manufacturing problems," said Raul Camposano, Synopsys' chief technology officer, senior vice president and general manager of the Silicon Engineering Group.
"This makes PrimeYield LCC's link to IC Compiler extremely valuable for increasing designers' efficiency and helping accelerate time to entitled yield for leading chipmakers such as Toshiba".
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
