Product category:
Design and Development Software
News Release from: Synopsys | Subject: Design Compiler topographical technology
Edited by the Electronicstalk Editorial
Team on 24 August 2006
Topographical technology shortens time
to market
Progate Group Corporation has adopted Synopsys' Design Compiler topographical technology to help accelerate time to market for its products.
Progate Group Corporation (PGC), one of the largest SoC/ASIC design service providers in Taiwan, has adopted Synopsys' Design Compiler topographical technology to help accelerate time to market for its products Topographical technology accurately predicts post-layout design performance early in the design cycle, enabling designers to identify and fix issues during RTL synthesis
This article was originally published on Electronicstalk on 16 May 2006 at 8.00am (UK)
Related stories
Reference methodology covers latest ARM processor
Available now from Synopsys is the ARM-Synopsys Galaxy Reference Methodology (RM) with support for Synopsys' Design Compiler topographical technology.
Korean chip designers get it right first time
ETRI has used Synopsys Design Compiler topographical technology to expedite the tapeout of its new 90nm multimedia chip.
By eliminating time-consuming iterations between RTL synthesis and physical layout, PGC designers are able to close on their performance goals quickly and more efficiently.
"Topographical technology streamlines the design process by giving our RTL designers visibility into post-layout design issues without having to learn or run physical implementation tools", said Jasper Lee, Technical Manager at PGC.
"The results we have seen using topographical technology correlate within 2 to 6% of actual layout timing and area".
"This tight correlation enables our designers to achieve desired performance faster, reducing total design time up to four weeks".
Topographical technology accurately predicts interconnect delays by utilising Synopsys' physical implementation technologies rather than approximations, also known as wire-load models.
In addition, topographical technology incorporates clock-tree synthesis technology to accurately estimate post-layout power consumption.
This extends topographical technology correlation beyond timing and area to include leakage and dynamic power.
"Topographical technology continues our strong tradition of bringing to market innovative synthesis technologies", said Antun Domic, Senior Vice President and General Manager of Synopsys' Implementation Group.
"Design Compiler customers are benefiting from a highly-correlated RTL-to-GDSII flow that significantly reduces their design cycle time and helps them stay competitive in today's market".
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
