Product category:
Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare for SMIC 130nm
Edited by the Electronicstalk Editorial
Team on 11 September 2006
Mixed-signal IP moves to 130nm process
Connectivity IP is designed for incorporation with Semiconductor Manufacturing International Corporation's 130nm technology.
Synopsys has expanded its DesignWare mixed-signal intellectual property (MSIP) portfolio with the release of connectivity IP for Semiconductor Manufacturing International Corporation's (SMIC's) 130nm technology The mixed-signal PHY IP supports the following protocols: USB, PCIe, SATA and XAUI
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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These PHYs are highly complex, process-tuned analogue interfaces used in today's high-volume, highly integrated mobile terminals, home entertainment, computing, storage and networking applications.
Additionally, high-performance DesignWare memory interface I/Os, such as DDR2 and mobile DDR, are available on SMIC's 130nm process.
DesignWare mixed-signal PHY IPs are extremely differentiated compared with other PHY IP solutions in the market.
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They consume the lowest amount of power in the industry at least 30% lower than competitive solutions.
This makes them ideal for mobile applications and saves on packaging costs.
The PHY IP is also designed to have the lowest area, noise and jitter performance in the industry.
It also features a uniquely robust architecture that makes it insensitive to process, voltage and temperature variations, helping ensure high yields.
Onboard diagnostics on the PCI Express, SATA and XAUI PHYs also enable inexpensive at-speed production testing that significantly reduces test-time budgets and costs.
"Synopsys has some of the highest performance and most differentiated mixed-signal IP on the market, and we are very pleased to announce our collaboration with them", said Paul Ouyang, Vice President of Marketing at SMIC.
"Together we can ensure that our customers have access to cost-effective, lowest power and lowest area USB 2.0 PHYs, serdes-based PHYs for PCI Express, SATA and XAUI, and memory interface I/Os such as DDR2 and mobile DDR in our industry-leading 130nm technology".
"With Synopsys, our customers can be assured of high-quality deliverables designed for low-risk system-on-chip (SoC) integration".
"We worked closely with SMIC to ensure that the low power and area of our PHYs and their high-yield characteristics are retained when manufactured in SMIC's 130nm process", said Guri Stark, Vice President of Marketing for the Solutions Group at Synopsys.
"We will continue collaborating with SMIC and aligning our mixed-signal IP roadmap with their technology roadmap to meet the demands of our mutual customers".
Synopsys DesignWare USB 2.0 nanoPHY IP, and DDR2 and mobile DDR memory interface I/Os are available now.
PCI Express, SATA and XAUI PHYs are expected to be available in Q4 of calendar 2006.
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