Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 20 September 2006
Donation opens access to power
management
Synopsys has donated power management technology to Accellera, the EDA organisation focused on electronic design automation standards.
Synopsys has donated power management technology to Accellera, the EDA organisation focused on electronic design automation standards The donation includes power management commands, SystemVerilog constructs, VHDL constructs, and the Switching Activity Interchange Format (SAIF), all in support of Accellera's Unified Power Format technical subcommittee's efforts
This article was originally published on Electronicstalk on 3 Apr 2007 at 8.00am (UK)
Related stories
Software verifies low-power features in new chips
Software ensures compliance with the widely supported Unified Power Format (UPF) 1.0 Accellera standard.
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
Tensilica standardises on Physical Compiler
Tensilica has standardised on Synopsys Physical Compiler and developed a high-performance reference flow around Physical Compiler for its Xtensa V processor cores.
Under the Unified Power Format activities, the design community, EDA tool suppliers and standards bodies are working together to produce an open and inclusive standard for low power design by January 2007.
"The donation by Synopsys to the Unified Power Format technical subcommittee is much appreciated and complements donations from other Accellera members", said Shrenik Mehta, Accellera Chair.
"We look forward to delivering a standard based on industry-wide contributions that will quickly meet the demands of end-customers".
Synopsys is an industry leader in providing solutions for low power design automation.
Its low power solutions have been proven through multiple successful advanced low power tapeouts to enable customers to develop more competitive products.
The Synopsys Galaxy and Discovery platform solutions for low power design span RTL synthesis, physical implementation, verification, and analysis.
This allows simulation of power-down blocks, equivalency and design-checking of advanced low power designs, inference of consistent constraints as early as possible, and communication of the designer's power intent throughout the entire design and verification flow.
"Many customers worldwide utilise Synopsys' low power technology to produce their most advanced low power designs", said Rich Goldman, Vice President of Strategic Market Development at Synopsys.
"By contributing our technology to the Accellera Unified Power Format technical subcommittee, Synopsys demonstrates its dedication to allow all designers and EDA suppliers to utilise its proven technology as a comprehensive standard for low power design".
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
