Product category:
Design and Development Software
News Release from: Synopsys | Subject: VCS
Edited by the Electronicstalk Editorial
Team on 05 October 2006
Testbench doubles verification
productivity
Enterasys Networks has selected the Synopsys VCS functional verification solution and its SystemVerilog Native Testbench following an extensive evaluation of available solutions.
Enterasys Networks, a provider of security-enabled network infrastructure products, has selected the Synopsys VCS functional verification solution and its SystemVerilog Native Testbench (NTB) following an extensive evaluation of available solutions Enterasys has adopted the VMM methodology, as defined in the Verification Methodology Manual (VMM) for SystemVerilog, to accelerate the creation of a powerful, efficient verification environment
This article was originally published on Electronicstalk on 1 Oct 2001 at 8.00am (UK)
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VCS 6.0.1 is the latest release of the industry's highest performance Verilog simulator from Synopsis.
Upgrade boosts verification performance
Synopsys has integrated its Vera and VCS tools to boost verification performance.
Enterasys created a SystemVerilog verification environment for a complex, multichip telecommunications router switch in significantly shorter time than previous designs, and with the VCS solution has uncovered bugs that remained undetected by legacy verification environments.
"Moving to a SystemVerilog-based verification flow with VCS NTB has doubled our verification productivity compared with previous projects", said Scott Scheeler, vice president of Engineering at Enterasys.
"The VMM methodology was of immeasurable help in getting us started with SystemVerilog and has enabled our team to build a complete, robust and scalable verification environment in just a matter of months".
Further reading
Triple the performance from latest simulators
Synopsys has unveiled the latest releases of its VCS Verilog simulator, VCS 6.1, and its high-performance Scirocco VHDL simulator, Scirocco 2001.10.
Simulator supports latest standardised Verilog
The latest release of the Synopsys VCS Verilog simulator, VCS 6.2, now supports the Verilog-AMS language through a technology platform called VCS DirectAMS.
Enterasys' complex system consisted of a custom ASIC and two large FPGAs, all of which are being verified with SystemVerilog.
Much of the design was from a previous generation product, but the verification team built the new testbench from scratch to take advantage of SystemVerilog's superior constrained-random verification capabilities as well as the VMM methodology's robust environment building blocks.
Enterasys took full advantage of the VCS solution's powerful constraint solver, specifying thousands of constraints with hundreds of variables to allow for complete control over the randomisation of instructions.
Despite being their first time using SystemVerilog or the VMM methodology, the Enterasys verification team became productive in under a month and finished their complete environment in less than six months.
Prior to adopting SystemVerilog, similar projects typically required larger teams working for a longer time to achieve similar results.
The team used the VMM methodology to build the environment incrementally, allowing early tests to be run shortly after the project started.
When completed, the SystemVerilog environment was much smaller and more concise than previous projects.
The team concluded they were more productive sooner with SystemVerilog and the VMM methodology than with their legacy environment.
"Enterasys' improved verification productivity provides clear evidence of the value of SystemVerilog and the VMM methodology with VCS NTB", said George Zafiropoulos, Vice President of Marketing, Verification Group at Synopsys.
"Higher verification productivity will give companies like Enterasys an increasing competitive advantage as designs grow larger and more difficult to verify".
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