Product category:
Design and Development Software
News Release from: Synopsys | Subject: PrimeTime
Edited by the Electronicstalk Editorial
Team on 06 October 2006
Standard cells support signoff analysis
tool
ARM Advantage, Metro and Sage-X standard cell libraries now support next-generation signal integrity signoff models based on Liberty Composite Current Source modelling technology.
ARM Advantage, Metro and Sage-X standard cell libraries, part of ARM's Artisan physical IP family, now support the next-generation signal integrity signoff models based on Liberty Composite Current Source (CCS) modelling technology Used in conjunction with the Synopsys PrimeTime analysis tool, the golden signoff standard, CCS noise models allow designers to get better accuracy and reduced turnaround time
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
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Synopsys has completed its RTL-to-GDSII flow by introducing two high-performance tools built into Physical Compiler: Route Compiler and ClockTree Compiler.
Liberty open source noise models also facilitate visibility into transistor-level behaviour that is key to nanometre signoff analysis.
CCS noise models are proven to deliver signoff level accuracy to within 2% of HSpice simulation as seen at leading semiconductor companies.
"Over the years, we have closely collaborated with Synopsys to advance design solutions based on open standards", said Brent Dichter, General Manager, ARM Physical IP.
Further reading
New modelling technologies benefit big SoC designs
The newest release of Synopsys PrimeTime includes significant performance improvements using new modelling technologies.
Crosstalk analysis extended to standard cells
Virtual Silicon eSi-Route standard cell libraries are now available for PrimeTime SI.
"Open-source CCS modelling technology has gained significant momentum in the semiconductor industry, and we look forward to once again leading in the IP industry with CCS noise support, the next generation signal integrity models".
CCS models are the industry's first open-source current-based models to unify timing, signal-integrity, and power.
CCS technology is designed to address the new low-power design challenges and the industry's advanced process modelling challenges for 65nm and below geometries.
Other noise models suffer from limited accuracy or employ closed, proprietary formats limiting their use during signoff.
In contrast, the CCS-based noise models are current-based and allow signoff tools to much more closely model actual silicon behaviour, thus reducing design iterations.
CCS noise models are open-source, giving users transparency and confidence during signoff and promoting interoperability across the EDA industry.
"In order for our customers to obtain the silicon entitlements of the latest processes, they need world class implementation and signoff tools as well as highest accuracy IP", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
"The Synopsys Galaxy Design Platform combined with CCS-enabled models from industry-leading IP providers such as ARM will help ensure that our mutual customers get their silicon to function as expected and meet their challenging nanometre requirements".
CCS timing and noise models for the ARM Advantage, Metro and Sage-X standard cell libraries are available for immediate download from the ARM website.
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