Product category:
Design and Development Software
News Release from: Synopsys | Subject: MinChip technology
Edited by the Electronicstalk Editorial
Team on 10 October 2006
Autorouter shrinks die sizes
Novel MinChip technology analyses physical design complexity and identifies the smallest routable size for semiconductor designs.
Novel MinChip technology analyses physical design complexity and identifies the smallest routable size for semiconductor designs The technology is integrated into the physical design flow in Synopsys' JupiterXT floorplanning tool and IC Compiler place-and-route solution
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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MinChip technology automates the process of identifying the smallest routable area for a design.
Optimal results are achieved in hours, saving weeks of manual effort while taking into account all potential area savings.
The new die size optimisation methodology enabled by MinChip delivers critical value for high-volume applications where even small area savings has a significant impact on overall cost per chip.
Synopsys' die size optimisation methodology delivers the smallest possible chip size at tapeout.
Following optimisation by IC Compiler, MinChip technology is applied to the design.
In hours, it returns a result that represents the minimum area in which the design can be implemented and remain routable while retaining the characteristics of the original floorplan.
The resulting design is then taken through the normal design closure process.
MinChip uses Synopsys' best-in-class placement and routing technologies to drive accurate routing prediction, ensuring correlation to the final physical design.
This new capability automates a task that otherwise requires complex scripts and countless implementation runs to reach the same result.
For high volume applications, modest area savings can represent a significant yield improvement.
In internal testing at Synopsys using customer taped out designs, average area reductions of 9% were observed.
"The benefit of being able to implement a design at the smallest chip size for high-volume applications is clear", said Antun Domic, Senior Vice President and General Manager, Implementation Group, Synopsys.
"Die size optimisation enabled by JupiterXT and IC Compiler allows designers to incorporate an area-optimisation step into their tapeout schedule with minimal effort and the possibility of huge payback because of the reduced area".
"Once again, Synopsys is raising the bar by delivering higher designer productivity at the lowest possible cost per chip".
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