Product category:
Design and Development Software
News Release from: Synopsys | Subject: Test reference design flow
Edited by the Electronicstalk Editorial
Team on 24 October 2006
Test reference flow checks on-chip
memory
Synopsys and Virage Logic Corp have announced initial availability of a test reference design flow for cost-effective testing and repair of embedded memories for system-on-chip (SoC) designs.
Synopsys and Virage Logic Corp have announced initial availability of a test reference design flow for cost-effective testing and repair of embedded memories for system-on-chip (SoC) designs The validated test design flow for 90 and 65nm processes is based on the Synopsys Galaxy test platform and Virage Logic's Self-Test and Repair (STAR) Memory System
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The reference design flow provides designers an automated and comprehensive solution to address time to market pressures and challenges of creating high-quality manufacturing tests for complex designs that contain multiple embedded memories.
The collaboration will continue with a second validated Galaxy test reference flow, which will integrate the testing of Synopsys DesignWare IP memories within Virage Logic's STAR Memory System.
"This latest collaboration with Synopsys further validates Virage Logic's commitment to providing customers with integrated design flows that help accelerate their silicon success, particularly as they move to the more advanced process nodes of 90nm and 65nm", said Jim Ensell, Senior Vice President of Marketing and Business Development at Virage Logic.
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"With STAR Memory System customers achieving yield improvements of up to 250%, we're confident the new Synopsys-Virage Logic reference design flow will enable our mutual customers to meet their SoC test, yield, and time to market goals".
"Today's consumer products often contain dozens if not hundreds of memories and register files", said Bijan Kiani, Vice President of Marketing, Synopsys Implementation Group.
"Creating high-quality manufacturing tests that deliver good coverage for the design logic as well as the memory content is a challenging and time-consuming task".
"The Synopsys-Virage Logic collaboration will help designers address these challenges by ensuring interoperability between Virage Logic's STAR Memory System RTL flows and the test synthesis flows within Synopsys' Galaxy test platform".
"Synopsys customers using DFT MAX physical-aware scan compression to reduce test costs and increase test quality will now benefit from a verified, automated flow that includes comprehensive testing of embedded memories".
A reference design and detailed application note describing the test reference flow will be available this quarter on Synopsys' SolvNet online support site.
The STAR Memory System and supporting products are currently available from Virage Logic.
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