Product category:
Design and Development Software
News Release from: Synopsys | Subject: DFT MAX
Edited by the Electronicstalk Editorial
Team on 23 November 2006
Compression reduces Sanyo's test data by
90%
Sanyo Semiconductor has adopted the Synopsys DFT MAX scan compression automation solution to further increase the test quality of its digital designs.
Sanyo Semiconductor has adopted the Synopsys DFT MAX scan compression automation solution to further increase the test quality of its digital designs Using DFT MAX, Sanyo engineers reduced test data volume by more than 90%, enabling them to achieve their high-quality test goals in less time
This article was originally published on Electronicstalk on 8 Nov 2005 at 8.00am (UK)
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DFT MAX takes advantage of physical-aware links within the Synopsys Galaxy Design Platform, enabling designers to avoid costly iterations and achieve rapid design closure.
Sanyo's engineers required the flexibility to generate many more patterns, if needed, to reach the highest-quality at-speed testing of their large-scale integration (LSI) circuits.
However, they realised increasing the quality would lead to a larger volume of test data without an effective way to compress the data to fit within tester memory constraints.
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"We found that we could meet our high-quality goals by adding DFT MAX to our Galaxy Design Platform flows", said Hiroyuki Oike, General Manager of Sanyo's System Solutions Business Division.
"After thoroughly evaluating DFT MAX to implement on-chip compression, we decided to adopt it for all our future LSI designs".
Sanyo designers wanted a solution that would not only meet their compression goals, but would also be as easy to implement as traditional scan.
DFT MAX's ease-of-use, combined with its seamless integration with other flows in the Galaxy Design Platform, allowed Sanyo designers to quickly migrate to DFT MAX and achieve greater than 90% digital test data volume reduction for two LSIs: a 4-million-gate communication chip and a 2-million-gate digital imaging chip.
For each of these designs, DFT MAX needed just 0.1% and 0.2% additional gates for compression.
"We adopted DFT MAX because we were able to improve the quality for our complex designs and achieve this with less test data volume and less test time", said Yuji Shiine, Digital Design Section Manager in Sanyo's Design Engineering Department.
"And migrating to DFT MAX was easy because it required little effort to integrate it into our existing DFT Compiler flows".
"As a result, we are going to use DFT MAX with the other solutions in Synopsys' Galaxy Design Platform in our effort to continually improve the quality and technical differentiation of our products".
"Sanyo's adoption of DFT MAX further validates the need for a compression solution that is simple to implement and does not impact the physical implementation of the chip", said Graham Etchells, Director of Test Marketing, Synopsys Implementation Group.
"Our customers are seeing immediate and substantial return-on-investment using DFT MAX because the tool is easy to use and achieves highly predictable compression results".
"Also, since DFT MAX takes advantage of physical-aware links within the Galaxy Design Platform, it has negligible timing and area impact on the physical implementation of the chip, enabling rapid design closure".
"In contrast, compression architectures that require sequential logic can require many more iterations to converge on timing and take much longer to achieve design closure".
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