Product category:
Design and Development Software
News Release from: Synopsys | Subject: Galaxy design platform
Edited by the Electronicstalk Editorial
Team on 06 December 2006
Cypress deploys Synopsys PrimeRail
Synopsys has announced that Cypress Semiconductor has successfully taped out its West Bridge Antioch peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC)
to speed tapeout of mobile phone IC design Smiconductor design software company Synopsys has announced that Cypress Semiconductor has successfully taped out its West Bridge Antioch peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy design platform RTL-to-GDSII low-power solution, including PrimeRail dynamic power network analysis The multi-threshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimised standby current
This article was originally published on Electronicstalk on 5 Feb 2003 at 8.00am (UK)
Related stories
Complete platform covers advanced IC design
The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools, to enable advanced IC design.
Test solution aids core-based design development
Synopsys has added a comprehensive test automation solution for core-based designs to its DFT Compiler, a key component of the Galaxy design platform.
PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation.
"For our mobile phone chip design we needed a solution that could address peak current problems related to the use of Power Gating switches," said Nagendra Cherukupalli, vice president of Asia Pacific design centres and chip integration at Cypress.
"Synopsys' PrimeRail and its integration with the Galaxy design platform enabled our designers to analyse power integrity issues of the power gating switches and decoupling capacitors prior to tapeout".
Further reading
Analyser speeds to faster timing signoff
The latest release of PrimeTime - the timing backbone in Synopsys' Galaxy design platform - has set a new standard for performance in static timing analysis and signoff of multi-million-gate designs.
Tools form basis of TSMC Reference Flow
The Galaxy Design Platform and other Synopsys tools have been integrated into TSMC's advanced Reference Flow 4.0.
Built on Synopsys' gold-standard Star-RCXT extraction and PrimeTime sign-off technologies, PrimeRail offers full-chip analysis, dynamic memory and macro-modelling capabilities for advanced multi-voltage, low-power, high-performance designs.
Its multimode analysis capability enables users to pinpoint and mitigate problems with critical power-up rush current or excessive current during wake-up to active mode in MTCMOS designs.
PrimeRail is integrated with the Galaxy design platform, allowing designers to predict voltage drop during floorplanning, perform pre- and post-layout analysis with on-chip decoupling capacitance, and achieve full-chip sign-off with package parasitics.
"Cypress has once again placed their confidence in Synopsys' comprehensive low-power solution," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group.
"PrimeRail's analysis capabilities are an extension of our low-power leadership, and the power network solution is the latest in our efforts to constantly strengthen Synopsys offerings".
"The Cypress project demonstrates our commitment to addressing the growing challenges designers face with low-power design, particularly in the areas of mobile and wireless applications".
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