Product category:
Design and Development Software
News Release from: Synopsys | Subject: Design Compiler
Edited by the Electronicstalk Editorial
Team on 14 December 2006
Topographical technology in new 65nm
methodology
Semiconductor Technology Academic Research centre has deployed Synopsys Design Compiler topographical technology in its 65nm Synopsys Galaxy Design Platform-based design flow
Synopsys has announced that the Semiconductor Technology Academic Research centre (STARC) has deployed Synopsys Design Compiler topographical technology in its 65nm Synopsys Galaxy Design Platform-based design flow (project name: Eagle Flow) in the Starcad-CEL methodology Topographical technology accurately predicts post-layout design performance such as timing, power, and area early in the design cycle, enabling designers to identify and fix issues during RTL synthesis
This article was originally published on Electronicstalk on 29 May 2002 at 8.00am (UK)
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By helping to eliminate time-consuming iterations between RTL synthesis and physical layout to achieve design closure, topographical technology assists designers in closing on their performance goals quickly and more efficiently.
"Tight correlation between synthesis and layout is crucial to achieving design closure quickly and efficiently," said Nobuyuki Nishiguchi, vice president and general manager, Development Department-1 at STARC.
"By implementing topographical technology in our 65nm design flow, we achieved an 11x improvement in turnaround time while meeting our stringent high-speed, low-power performance requirements".
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"And, as part of the Galaxy Design Platform, topographical technology was very easy to adopt in the new Starcad-CEL RTL-to-GDSII design methodology".
In addition to productivity improvements, the Galaxy Design Platform-based Eagle flow also supports a range of advanced capabilities addressing test, hierarchical clock planning, and low-power design.
To achieve the 11x improvement over the previous-generation design flow, STARC introduced Design Compiler topographical technology into its Starcad-CEL methodology which also includes IC Compiler for physical implementation, DFT MAX for test compression, the CCS library format for cell library modelling, and the golden PrimeTime SI sign-off solution for timing.
Design Compiler topographical technology is an innovative, tapeout-proven synthesis technology that utilises the Galaxy Design Platform physical implementation technologies to derive interconnect delays.
This delay data allows the Design Compiler solution to predict post-layout design results such as timing, testability, and area during synthesis.
Topographical technology also utilises clock tree synthesis technology to estimate post-layout power consumption of the design.
"We are seeing very rapid adoption of Design Compiler topographical technology by customers worldwide because it can significantly improve their productivity," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group.
"The majority of leading design houses in Japan utilise methodologies developed by STARC; now they can reap the benefits of using topographical technology as part of STARC's STARCAD-CEL release".
STARC is a research consortium of major Japanese semiconductor companies developing leading-edge system-on-chip (SoC) design methodologies.
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