Product category:
Design and Development Software
News Release from: Synopsys | Subject: VCS
Edited by the Electronicstalk Editorial
Team on 09 January 2007
Functional verification speeds
SuperHyway bus SoCs
Renesas Technology Corp has adopted the VCS functional verification solution for the development of complex SoCs.
Renesas Technology Corp, one of the world's leading semiconductor system solutions providers for mobile, automotive and PC/AV (audio visual) markets, has adopted the VCS functional verification solution for the development of complex SoCs In addition, Renesas has adopted the VMM methodology, as defined in the Verification Methodology Manual (VMM) for SystemVerilog, for the creation of advanced SoC verification environments
This article was originally published on Electronicstalk on 1 Oct 2001 at 8.00am (UK)
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Renesas used the VCS solution with the VMM methodology to verify its critical SuperHyway bus on-chip interconnect infrastructure.
"We have adopted VCS, SystemVerilog and the VMM methodology for our next generation of advanced SoC verification environments", said Kazunobu Morimoto, Group Manager, System Level Design and Verification Technology Department at Renesas.
"SystemVerilog and the VMM methodology have proven easy to adopt and deploy with the VCS solution, and will enable significant improvements in verification productivity in our SoC designs using the SuperHyway bus".
Further reading
Triple the performance from latest simulators
Synopsys has unveiled the latest releases of its VCS Verilog simulator, VCS 6.1, and its high-performance Scirocco VHDL simulator, Scirocco 2001.10.
Simulator supports latest standardised Verilog
The latest release of the Synopsys VCS Verilog simulator, VCS 6.2, now supports the Verilog-AMS language through a technology platform called VCS DirectAMS.
The SuperHyway bus is a VSIA/VCI compliant on-chip interconnect infrastructure designed to give developers a scalable high-bandwidth, low-latency interconnect.
Renesas needed to improve the productivity and predictability of the SuperHyway bus verification environment to keep up with growing demand for new system components.
Their new environment needed to reuse legacy tests, enable detailed verification-progress tracking using coverage, and allow for easy addition, modification and maintenance.
Over a period of nine months, Renesas engineers learned the SystemVerilog language and the VMM methodology and built a comprehensive verification environment for the SuperHyway bus running in the VCS solution.
Key components of the environment included assertion-based protocol checkers, transaction checkers and scoreboards, transaction-level initiator and target models, coverage descriptions and a legacy test interface.
All components were built using SystemVerilog and followed the VMM methodology.
Renesas realised many benefits, including higher verification productivity with the transaction-level modelling and constrained-random, coverage-driven capabilities of the VMM methodology, as well as the ability to easily reuse legacy tests.
In addition, the verification code base for the new environment was one-third smaller than the legacy environment and was easier to maintain and extend for new projects due to the VMM methodology's clean, layered architecture.
"Renesas has proven that SystemVerilog and the VMM methodology can greatly improve verification productivity, while being easy to adopt and deploy", said George Zafiropoulos, Vice President of Marketing, Verification Group at Synopsys.
"The VCS solution's superior support for SystemVerilog and the VMM methodology make it the preferred choice for companies looking to move to higher levels of verification productivity and predictability".
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