Product category:
Design and Development Software
News Release from: Synopsys | Subject: DFT MAX
Edited by the Electronicstalk Editorial
Team on 18 January 2007
Compression software expands Oki's test
coverage
Oki Electric has adopted the Synopsys DFT MAX scan compression automation solution to enable higher test quality for its digital designs.
Oki Electric has adopted the Synopsys DFT MAX scan compression automation solution to enable higher test quality for its digital designs DFT MAX implements compression on-chip that results in significantly less data required for each test pattern
This article was originally published on Electronicstalk on 8 Nov 2005 at 8.00am (UK)
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Using DFT MAX, Oki was able to apply comprehensive at-speed testing in addition to its regular tests to improve the quality of volume testing without having to increase the memory capacity of its testers.
"Oki needed a solution to further improve the product quality of our complex systems-on-chips (SoCs), but do so in a cost-effective manner that would allow us to utilise our existing automatic test equipment", said Jiro Kobayashi, Senior Manager of Oki's Telecom and Automotive System business division in Silicon Solutions Company.
"DFT MAX substantially reduced the amount of data needed for our at-speed tests, using a very low area overhead and requiring very little additional design effort to incorporate into our existing DFT flows".
Further reading
Design for test saves wireless IC costs
Wireless IC specialist CSR has successfully used Synopsys' DFT MAX to reduce digital tester costs.
Scan compression automation proves popular
DFT MAX scan compression automation solution has been instrumental in reducing test costs related to data inflation on more than 50 successful tapeouts since its general release in September 2005.
Compression reduces Sanyo's test data by 90%
Sanyo Semiconductor has adopted the Synopsys DFT MAX scan compression automation solution to further increase the test quality of its digital designs.
"For these reasons, Oki has adopted DFT MAX for our future SoC designs".
Very high quality testing can be achieved by applying tests at a chip's operating frequency.
But if different circuits operate at different frequencies, it can be a difficult and time-consuming task to design and verify custom logic to control the complex clock sequencing.
This was the challenge faced by designers of a several-million-gate Oki communications SoC containing circuits driven by a large number of internal and external clocks operating at different frequencies.
Rather than develop a custom clock controller from scratch and risk delaying the project schedule, Oki designers instead used DFT MAX to fully synthesise the clock controller circuits and integrate them into the design.
This automated approach saved a significant amount of engineering time and effort, and made it possible to tapeout the design on time.
Synopsys' TetraMAX DSMTest automatic test pattern generation (ATPG) solution was later used to generate high-coverage transition delay patterns which were applied successfully on the tester to validate the fabricated device.
"As designs have grown larger and more challenging to test, semiconductor companies such as Oki are turning to Synopsys for the most innovative DFT solutions", said Graham Etchells, Director of Test Marketing, Synopsys Implementation Group.
"DFT MAX helps these companies achieve their quality goals with minimal impact on design time and silicon cost".
"And because migration to DFT MAX can be accomplished in days instead of months, our customers quickly see tangible benefits from applying more defect-based tests-transition delay, bridging, IDDQ, and now small delay defect tests-to achieve even higher test quality and higher diagnostics accuracy".
Using DFT MAX requires no expertise in test compression techniques.
Its gates-only adaptive scan architecture is the most area-efficient solution available.
By avoiding the use of complex sequential state machines for compression/decompression, the adaptive scan architecture disperses test logic throughout the design, alleviating wire-routing congestion and reducing silicon area overhead cost.
Working seamlessly within Synopsys' Galaxy Design Platform, DFT MAX produces predictable results with little to no impact on timing.
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