Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 12 February 2007
Mplicity uses Formality for equivalence
checking
Mplicity, a specialist in multicore IC design implementation, has standardised on Synopsys equivalence-checking software and retiming verification for customers of Mplicity's CoreUpGrade offering.
Mplicity, a specialist in multi-core IC design implementation, has standardised on the Synopsys Formality equivalence-checking software and its retiming verification methodology for customers of Mplicity's CoreUpGrade product The Formality software extends the reach of equivalence-checking technology to provide comprehensive verification that addresses complex design optimisations
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
Related stories
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
Tensilica standardises on Physical Compiler
Tensilica has standardised on Synopsys Physical Compiler and developed a high-performance reference flow around Physical Compiler for its Xtensa V processor cores.
"Mplicity's "CoreUpGrade" product seamlessly transforms a given single-processor core into an enriched multicore, boosting silicon performance while reducing chip size and power consumption", says Eran Dagan, chief technology officer at Mplicity.
"Register retiming is a significant part of the CoreUpGrade process and Synopsys' Formality verification technology excelled in its ability to verify this and other optimisations for our customers".
The Synopsys retiming verification methodology uses enhanced solver technologies to account for combinational changes that may have occurred during implementation.
This methodology extends the reach of verification into spaces previously thought unverifiable by equivalence-checking technology.
Synopsys collaborated with Mplicity to ensure that the multicore verification flow records the retiming and other data so that designers can verify all aspects of their multicore design implementation flow.
"There has long been a gap between the level of design optimisation achieved during implementation and what equivalence-checking technology could readily verify", says Antun Domic, senior vice president and general manager, Synopsys Implementation Group.
"The Formality-guided methodology safely closes this gap, allowing for significant improvements in design quality without sacrificing verifiability".
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
