Product category:
Design and Development Software
News Release from: Synopsys | Subject: Synopsys Design Compiler
Edited by the Electronicstalk Editorial
Team on 14 February 2007
Design Compiler boosts ASIC development
STMicroelectronics has deployed Synopsys Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to speed up design time.
STMicroelectronics has deployed Synopsys Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to speed up design time Using Design Compiler topographical technology in its ASIC methodology will help the chip maker to eliminate design iterations and streamline the overall design cycle for its internal design groups and for external customers
This article was originally published on Electronicstalk on 23 Oct 2006 at 8.00am (UK)
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Semiconductor Technology Academic Research centre has deployed Synopsys Design Compiler topographical technology in its 65nm Synopsys Galaxy Design Platform-based design flow
In an ASIC model, reducing netlist iterations between the customer and ASIC vendor to achieve design closure is critical to completing a design on schedule.
Design Compiler topographical technology accurately predicts final design timing, power, testability and area results prior to actual physical implementation, giving front-end designers early visibility into layout results.
In this way, both the customer and ASIC vendor can be assured that the netlist generated after synthesis will, in fact, achieve the desired performance.
Further reading
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Casio has adopted Synopsys Design Compiler topographical technology to shorten the design schedule for its next generation Exilim digital camera chips.
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
"Topographical technology offers much-needed predictability for a convergent RTL-to-GDSII path".
"Front-end designers no longer have to wait for layout results to uncover critical design issues; they can identify and fix them up front".
"In turn, back-end teams receive a better netlist for physical implementation which is more likely to meet the desired performance", says Philippe Magarshack, group vice president, Central CAD and Design Solutions, Front-End Technology Manufacturing, at STMicroelectronics".
"We are extremely pleased with the results we have seen with topographical technology on advanced ASIC designs and have incorporated it in both our 90 and 65nm ASIC design flows".
"We encourage our internal and external ASIC customers to use it for all their synthesis needs to expedite the design process".
Design Compiler uses the Galaxy Design Platform physical implementation technologies to derive accurate interconnect delay data that allows Design Compiler to predict post-layout design results such as timing, testability, and area during synthesis.
In addition, topographical technology uses clock tree synthesis technology to estimate post-layout power results of the design, resulting in a highly predictable RTL-to-GDSII path".
"More and more market leaders like STMicroelectronics are recognising the value of Synopsys topographical technology to help streamline their design flows and reduce design cycle time", says Antun Domic, senior vice president and general manager, Synopsys Implementation Group".
""We look forward to extending our collaboration with STMicroelectronics to support their ASIC customers through the broad deployment of topographical technology".
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