Product category:
Design and Development Software
News Release from: Synopsys | Subject: Proteus optical proximity correction software
Edited by the Electronicstalk Editorial
Team on 01 March 2007
OPC software optimised for Intel Core
servers
Optical proximity correction (OPC) software has achieved substantial processor and memory improvements when optimised for and deployed on Intel Core microarchitecture-based server products.
Synopsys Proteus optical proximity correction (OPC) software has achieved substantial processor and memory improvements when optimised for and deployed on Intel Core microarchitecture-based server products Compared to competitive tools running on special-purpose custom platforms, Proteus has demonstrated price/performance superiority on Intel architectures, such as the Intel Dual-Core Xeon Processor 5100 series (formerly called Woodcrest), enabling chipmakers to significantly lower their turnaround time (TAT) and overall cost of ownership (CoO)
This article was originally published on Electronicstalk on 26 Feb 2004 at 8.00am (UK)
Related stories
Optical proximity correction software runs faster
Synopsys has significantly improved the performance of its Proteus optical proximity correction software through its distributed processing capability on the Intel Xeon architecture.
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
Tensilica standardises on Physical Compiler
Tensilica has standardised on Synopsys Physical Compiler and developed a high-performance reference flow around Physical Compiler for its Xtensa V processor cores.
This translates into a significant CoO advantage for Proteus OPC users.
Unlike alternative approaches involving custom hardware, optimised general-purpose platforms offer a high degree of flexibility -- an essential consideration, as the overall cost of computing is becoming an increasingly vital concern for chipmakers.
Users can deploy the same solution throughout their design-to-silicon flow, whether in back-end steps such as OPC, lithography rule checking (LRC) and mask data preparation (MDP), or in design-rule checking (DRC) and other front-end design applications.
Anantha Sethuraman, Vice President of Marketing, Design for Manufacturing, at Synopsys, "Our proven Proteus OPC engine has been in production for 10 years over seven consecutive technology nodes, delivering an average software performance improvement of 40% from year to year".
"Its innovative dual-domain engine further advances our commitment to lower customers' CoO by enabling a 50-% reduction in Proteus' memory footprint per compute node".
"When combined with optimised general-purpose computers, which are on their own steep price/performance improvement path, we believe this solution constitutes the most cost-effective strategy for high-volume manufacturing of 45nm and smaller devices".
"Optimised tools, such as Synopsys Proteus, can take advantage of the significant performance, power efficiency and value advantages offered by the Intel Xeon 5100 series processors", says Martin J Menard, Director, Platform Capabilities, Intel IT.
"Intel Core microarchitecture-based server platforms offer a cost-effective high performance computing solution in today's demanding chip manufacturing environment".
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
