Product category:
Design and Development Software
News Release from: Synopsys | Subject: DFT MAX
Edited by the Electronicstalk Editorial
Team on 08 March 2007
Compression cuts costs of nanometre
testing
Scan compression automation results in a 90% reduction in tester related costs.
Actions Semiconductor has adopted the Synopsys DFT MAX scan compression automation solution for its 0.13um SoC designs, resulting in a 90% reduction in tester related costs DFT MAX implements scan data compression on chip to significantly reduce the amount of test time and test data required to execute high quality manufacturing tests
This article was originally published on Electronicstalk on 8 Nov 2005 at 8.00am (UK)
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"As the leading supplier of portable multimedia player SoCs, Actions' products are designed into a vast range of portable consumer electronics worldwide".
"Our design team needed a proven compression solution that was easy to use and could decrease the costs of testing our next generation PMP SoCs", said Shawn Lee, Chief Technology Officer of Actions Semiconductor.
"We quickly got DFT MAX working on a multi-million-gate design thanks to its tight integration in the Synopsys Galaxy Design Platform".
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Scan compression automation proves popular
DFT MAX scan compression automation solution has been instrumental in reducing test costs related to data inflation on more than 50 successful tapeouts since its general release in September 2005.
"DFT MAX achieved more than 90% compression with an overhead of less than 500 extra gates".
"For these reasons, Actions has adopted DFT MAX for our future SoC designs".
Traditional test patterns are ineffective at detecting many timing sensitive defects, so semiconductor companies are now using transition delay tests to cover these defects at 0.13um geometries and below.
Applying both types of tests has led to an explosion in the total number of test patterns required to properly test a device, even as design complexity has increased.
The resulting inflation in both pattern count and test data volume per pattern has increased the time required to test each device, creating bottlenecks in production testing.
DFT MAX automatically implements compression on chip to substantially reduce test data volume and test application time while minimising the impact on silicon area.
"Actions' decision to use DFT MAX to help meet its quality and cost goals is testimony to the effectiveness of Synopsys' Galaxy test solutions", said Graham Etchells, Director of Test Marketing, Synopsys Implementation Group.
"Semiconductor companies like Actions require a fast path to lowering the costs of testing nanometre designs, and DFT MAX is the compression solution they are adopting to significantly reduce test data volume, application time and cost without impacting downstream physical design flows".
Using DFT MAX requires no expertise in test compression techniques.
Its gates only adaptive scan architecture is the most area efficient solution available.
By avoiding the use of complex sequential state machines for compression/decompression, the adaptive scan architecture disperses test logic throughout the design, alleviating wire routing congestion and reducing silicon area overhead cost.
Working seamlessly within Synopsys' Galaxy Design Platform, DFT MAX produces predictable results with little to no impact on timing.
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