Product category:
Intellectual Property Cores
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 12 March 2007
Serdes wins product of the year award
Serdes-based PHYs for PCI Express, SATA and XAUI have been awarded best connectivity intellectual property for 2006
AnalogueZone, a premier information source for electronic design engineers, has chosen Synopsys' DesignWare serdes-based PHYs for PCI Express, SATA and XAUI as the best connectivity intellectual property (IP) AnalogZone announced the selection in its Products of the Year 2006 issue published in February of this year
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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"Synopsys has taken a fresh look at serdes technologies and delivered a high-performance core that consumes half the power of a traditional design", says AnalogZone's Section Editor Lee Goldberg in the award announcement.
"This dedication, combined with Synopsys' rich self-diagnostic features, makes Synopsys' PHYs an ideal choice for PCIe, SATA or XAUI interfaces".
Synopsys' mixed-signal serdes IP is part of Synopsys' complete portfolio of DesignWare cores, digital controllers and verification IP, which fully support the PCIe, XAUI and SATA standards.
These high performance, mixed-signal PHYs offer highly differentiated, advanced built-in diagnostics for evaluating link performance and margin.
The PHYs are designed using a robust architecture that tolerates process, voltage and temperature variations without compromising performance.
Synopsys' silicon-proven IP provides an optimised, lower-risk, single-vendor solution, and enables low power and reduced area design in systems-on-chips (SoCs) that use these high-performance standards.
"We are honoured to receive this award from AnalogZone for our High Performance serdes-based IP", says John Koeter, Group Director for IP Marketing at Synopsys.
"The innovative design significantly reduces chip power and test time while our complete solution - which includes the digital, physical and verification IP for the PCIe, SATA and XAUI protocols - provides faster time to market".
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