Product category:
Design and Development Software
News Release from: Synopsys | Subject: Composite Current Source (CCS) models
Edited by the Electronicstalk Editorial
Team on 02 April 2007
Timing and noise models work with Galaxy
platform
Two design software companies team up to include high-accuracy CCS timing and noise models in the Galaxy design platform
Synopsys and Virage Logic have announced support of Composite Current Source (CCS) models for all advanced process-node versions of Virage Logic's Self Test and Repair (STAR) Memory, Area, Speed and Power (ASAP) Memory and ASAP Logic Standard Cell product lines Used in conjunction with the Synopsys Galaxy Design Platform, the high-accuracy CCS timing and noise models allow the designer to reduce guard-band margins during design implementation and sign-off, thus improving design performance and reducing design iterations
This article was originally published on Electronicstalk on 9 Apr 2007 at 8.00am (UK)
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CCS models are proven to deliver sign-off level accuracy to within 2% of HSPICE simulation as seen at leading semiconductor companies.
Virage Logic will be presenting the details of its CCS-supported semiconductor intellectual property (IP) product portfolio as part of the CCS technology tutorial at the Synopsys Users' Group (SNUG) San Jose meeting on 3rd April.
"Customers look to Virage Logic for silicon-proven, high-quality semiconductor IP, particularly as they move to the advanced process geometries of 65nm and below", says Ken Potts, Vice President of Product Marketing at Virage Logic.
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"CCS models provide the accuracy and flexibility needed to model our advanced process-technology memory and standard-cell products to ensure our customers can proceed with confidence on their complex SoC designs".
CCS modeling technology, part of the open-source Liberty library modeling standard, enables highly accurate and comprehensive modeling of nanometer effects that encompass timing, signal integrity and power.
CCS modeling technology is very adaptable, allowing for non-linear voltage or temperature scaling as well as the modeling of process variation.
CCS models simplify advanced low-power design flows such as multi-Vt and multi-Vdd, as well as dynamic voltage and frequency scaling.
There is significant industry- wide momentum behind CCS modeling technology with library availability from all leading IP vendors, foundries and integrated device manufacturers (IDMs).
"Our customers need world-class design implementation solutions coupled with high-accuracy, silicon-proven IP", says Bijan Kiani, Vice President of Marketing, Synopsys Implementation Group.
"CCS-supported semiconductor IP from a leading provider such as Virage Logic used in conjunction with the Synopsys Galaxy Design Platform is a recipe for success for our mutual customers".
CCS timing and noise models are expected to be available for all Virage Logic's advanced process node products beginning in Q3 calendar 2007.
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