Product category:
Design and Development Software
News Release from: Synopsys | Subject: Support for UPF 1.0 Accellera standard.
Edited by the Electronicstalk Editorial
Team on 03 April 2007
Software verifies low-power features in
new chips
Software ensures compliance with the widely supported Unified Power Format (UPF) 1.0 Accellera standard.
Synopsys is enhancing its comprehensive low-power verification and implementation software to ensure compliance with the widely supported Unified Power Format (UPF) 1.0 Accellera standard Proven by over 20 successful multivoltage tapeouts, the Synopsys system spans the entire low-power design flow from hardware/software power trade-off at the system level through simulation and static verification of low-power intent, complete low-power RTL-to-GDSII implementation and sign-off, and a comprehensive set of low-power intellectual property (IP)
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The enhanced support for UPF 1.0 is expected to be available in the second half of 2007.
The Discovery Verification Platform performs low-power verification from system to RTL to transistor level.
The Discovery platform enables power-aware simulation, formal equivalence checking, and static analysis of designs that use modern low-power techniques including multiple power domains, level shifters, isolation cells, and retention memory elements.
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The platform ensures correct operation of power-sensitive analogue, memory, and custom-digital designs through automatic detection of leakage paths, analysis of dynamic IR drop, and functional verification of complex power management circuitry.
The Galaxy Design Platform delivers the lowest power consumption, highest design performance and highest productivity through its complete low-power portfolio.
It includes the most advanced low-power techniques, such as multi-voltage and MTCMOS power gating, as well as more commonly used techniques such as clock gating and multi-threshold libraries.
In addition, it performs comprehensive dynamic and leakage power optimisation and analysis throughout the synthesis, physical design and sign-off phases of the design process.
Synopsys DesignWare IP is designed for low power consumption in both active and standby modes.
This is achieved by using power-efficient transmitters, phase-locked loop (PLL) blocks and clock gating techniques.
Synopsys' USB 2.0 nanoPHY, designed for the latest mobility devices, consumes half the power of previous USB implementations.
The PCI Express, Serial ATA (SATA), and XAUI high-speed serialiser / deserialiser (Serdes) PHY IP support low-power modes and consume significantly less power than similar IP on the market.
UPF 1.0 was created in response to customer demand for a standard that enables consistent and interoperable end-user low-power flows and methodologies.
Built upon proven technologies donated to Accellera by key players in the electronic design automation (EDA) and low-power semiconductor markets, UPF delivers productivity gains and simplification of low-power design flows.
"Increasing our customers' market competitiveness has been a key driver for us in developing our low-power solution", says John Chilton, Senior Vice President of Marketing and Business Development at Synopsys.
"Our Galaxy Design and Discovery Verification Platforms, complemented by a portfolio of low-power IP, offer our customers the comprehensive and advanced solution they need to quickly bring to market the most competitive low-power designs".
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