Product category:
Design and Development Software
News Release from: Synopsys | Subject: DesignWare Verification included in OCP-IP toolset
Edited by the Electronicstalk Editorial
Team on 16 April 2007
DesignWare Verification now in
consortium toolset
An EDA company is collaborating with a non-profit semiconductor industry consortium, to provide its verification IP as part of the consortium's verification toolset.
Synopsys is collaborating with Open Core Protocol International Partnership (OCP-IP), an independent non-profit semiconductor industry consortium, to provide Synopsys' DesignWare Verification IP (VIP) as part of OCP-IP's CoreCreator verification toolset DesignWare VIP for OCP, part of Synopsys' portfolio of standards-based verification IP, will become the OCP-IP endorsed verification IP tool and will replace the OCP bus functional models (BFM) currently provided with OCP's CoreCreator tool
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The new, combined system, which includes DesignWare VIP and CoreCreator's performance analysis, protocol checking, and transaction disassembly, gives OCP-IP members a common verification toolset, enabling maximum consistency and interoperability across OCP implementations.
The collaboration also further expands OCP-IP's robust thriving infrastructure.
"The inclusion of Synopsys' DesignWare VIP into CoreCreator is a natural extension of the significant contributions already made by Synopsys to OCP-IP", says Ian Mackintosh, President of OCP-IP.
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"DesignWare VIP for OCP enables us to provide our members with a best-in-class verification solution that is current with latest versions of the standard, together with support for the latest verification methodologies".
The Synopsys DesignWare VIP for OCP will be available to OCP-IP members on request from the OCP-IP website as part of their subscription entitlement.
Each release of the DesignWare VIP will be verified by OCP-IP for compliance to the latest version of the OCP standard.
Synopsys' DesignWare VIP for OCP includes 100% coverage of the functional coverage groups defined in section 4 of the OCP-IP compliance check document.
Synopsys' DesignWare VIP for OCP supports Verilog, VHDL and SystemVerilog test benches and is fully compliant with the Verification Methodology Manual (VMM) guidelines for coverage-driven, constrained-random verification environments.
It also supports the generation of trace files used by CoreCreator's OCP performance analysis, checker, and disassembly tools.
"When integrating IP in system-on-chip designs, one of the biggest challenges facing designers today is conformance to on-chip bus standards", says Ed Bard, Senior Director of IP marketing at Synopsys.
"Verification IP plays an extremely important role in minimising integration challenges by allowing designers to verify compliance of their interfaces".
"DesignWare VIP provides a consistent verification solution to the entire OCP-IP community, leading to maximised interoperability between OCP-IP member designs".
DesignWare Verification IP for OCP is available today and can be downloaded from the Synopsys IP directory.
OCP-IP members will be able to obtain licences of the DesignWare Verification IP for OCP within the second quarter of 2007 as part of their OCP-IP subscription.
A separate announcement will be broadcast to OCP-IP members at that time.
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