Product category:
Design and Development Software
News Release from: Synopsys | Subject: Design Compiler 2007
Edited by the Electronicstalk Editorial
Team on 23 April 2007
Design synthesis takes topographical
route
Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle.
The latest release of the Synopsys Design Compiler synthesis solution extends topographical technology to accelerate design closure for designs using advanced low power and test techniques, boosting designer productivity and IC performance Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Moreover, topographical technology supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100 times.
"Using topographical technology, the performance predictions made by synthesis correlated within 5% of physical implementation results", said Huang Tao, Design Manager at Hisilicon.
"Design Compiler 2007 additionally reduced chip area by an average of 5% while meeting the aggressive performance targets of our telecom designs".
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"Superior performance complemented by tight correlation to layout is exactly what our designers need to bring competitive products to market faster".
Topographical technology delivers tight correlation between performance results seen during synthesis and what is achieved after layout.
This eliminates the need for time consuming iterations between RTL synthesis and physical layout to achieve design closure.
Design Compiler shares technologies and infrastructure with the Galaxy Design Platform physical design solution to deliver a consistent and highly predictable RTL to GDSII path.
"We were faced with conflicting test goals at Cypress: we needed high test coverage but with very few dedicated test pins and limited memory on our legacy testers", said Don Smith, Design Director for the Data Communication Division at Cypress.
"We evaluated Synopsys' adaptive scan test compression technology, which took less than a day to adopt in our flow".
"Based on the results we've seen, we are confident that we can deliver the highest quality products while leveraging our existing test equipment infrastructure".
Design Compiler 2007 includes several innovative synthesis technologies such as adaptive retiming and power driven clock gating, to deliver an average 8% higher performance, 4% smaller area and 5% lower power consumption compared with the previous release.
In addition, the Synopsys Formality equivalence checking solution has been enhanced to independently and thoroughly verify these technologies, thereby allowing designers to achieve higher performance without sacrificing verification.
"In today's design environment, each design presents a unique set of implementation challenges that must be overcome to ensure predictable silicon success", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
"The advanced technologies in Design Compiler 2007 are helping designers meet their toughest performance targets while achieving the fastest and most predictable path to silicon".
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