Product category:
Design and Development Software
News Release from: Synopsys | Subject: Design Compiler
Edited by the Electronicstalk Editorial
Team on 09 May 2007
Topographical technology aids ASIC
layout
IBM has added support for topographical technology in its 90 and 65nm based application specific integrated circuit (ASIC) design kits.
IBM has added support for topographical technology in its 90 and 65nm based application specific integrated circuit (ASIC) design kits Synopsys' Design Compiler topographical technology enables IBM's ASIC customers to achieve tighter correlation between design results such as timing and power seen during synthesis and the results achieved after layout
This article was originally published on Electronicstalk on 29 May 2002 at 8.00am (UK)
Related stories
Faster-running RTL synthesis solution
Design Compiler 2002.05 is the latest and most powerful version of the RTL synthesis solution from Synopsys.
FPGA synthesis answers prototyping challenge
Design Compiler FPGA (DC FPGA) is a new FPGA synthesis product for designers who prototype ASICs using high-end FPGAs.
This eliminates the need for time consuming iterations between synthesis and layout to achieve design closure, thus significantly accelerating overall design time.
"We are pleased with the results we have seen with topographical technology".
"During our evaluation, synthesis results were consistently within five per cent of actual physical implementation results".
"The tight correlation between synthesis and layout is critical for a predictable RTL to GDSII flow", said Richard Busch, director of ASIC Products and Services at IBM Global Engineering Solutions.
"We have made topographical technology available in 90 and 65nm based design kits to speed up ASIC design time for our customers".
Design Compiler topographical technology shares technologies with the Galaxy Design Platform physical design solution to accurately predict final design results such as timing, area, testability and power during synthesis.
It enables RTL designers to foresee results after layout.
Using Synopsys' topographical technology based methodology, IBM's ASIC customers can take corrective measures to ensure that their design will achieve the required performance prior to sending the netlist to IBM for physical implementation.
Consequently, IBM receives a better quality netlist from its customers that speeds up physical implementation while meeting the required performance targets.
"A growing number of ASIC vendors are adopting topographical technology to streamline their design flow", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
"IBM's support enables its ASIC customers to reap the benefits of topographical technology in completing their most advanced ASICs much faster, with higher predictability and fewer iterations".
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

