Product category:
Intellectual Property Cores
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 17 July 2007
Acquisition to expand IP portfolio to
DDR
Synopsys is set to acquire the semiconductor IP assets of Mosaid Technologies, and will integrate these into its DesignWare IP portfolio.
Synopsys has signed a definitive agreement to acquire the semiconductor IP assets of Mosaid Technologies Synopsys plans to integrate such assets, consisting primarily of Mosaid's double datarate (DDR) memory controller and PHY semiconductor IP products, into its DesignWare IP portfolio
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The purchase will further increase the breadth of Synopsys' offerings in standards based connectivity IP.
The purchase price for the acquisition is approximately US $15 million, payable in cash.
The transaction is subject to customary closing conditions and is expected to close in August 2007.
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DDR DRAM is a key component in many electronic systems manufactured today, from set top boxes, high definition TVs, video cameras and printers to computing, networking and communications equipment.
With DDR2 DRAMs achieving speed grades up to 1067Mbit/s and DDR3 DRAMs going up to 1600Mbit/s, high performance DDR interfaces become a critical factor in overall system performance.
Timing and signal integrity issues can significantly complicate the design of DDR memory interfaces.
In the past, at speed grades of 500Mbit/s and below, many companies have implemented the DDR interface by stitching together components such as delay locked loops (DLLs) and phase locked loops (PLLs).
At DDR2 and DDR3 datarates, the same "roll your own" approach can cause designers to miss schedules or lower interface timing goals due to the difficulty in achieving timing closure.
To better address these challenges, designers need a complete, integrated solution consisting of digital DDR memory controllers and process specific mixed signal DDR PHY IP that are proven to work at the required datarates.
"The addition of Mosaid's DDR memory interface IP and engineering team will give our mutual customers access to a complete, high quality, silicon proven DDR IP solution for a broad set of process technologies", says Joachim Kunkel, Vice President and General Manager, Intellectual Property and System Level Solutions, Synopsys.
"With this acquisition, we continue to expand our industry leading portfolio of standards based connectivity IP so that our mutual customers can accelerate their time to market and minimise their design risk".
DDR2 and DDR3 memory interfaces are the latest additions to Synopsys' broad portfolio of standards based connectivity IP.
Synopsys' complete DesignWare DDR IP solution consists of digital memory controllers (protocol and memory controllers), hardened mixed signal DDR PHYs, and verification IP.
The combined product offering covers process nodes from 130 to 65nm in today's leading foundry processes.
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