Product category:
Design and Development Software
News Release from: Synopsys | Subject: Synopsys' Design Compiler Ultra
Edited by the Electronicstalk Editorial
Team on 05 September 2007
Design system chosen for GPS ICs
eRide switched to Design Compiler Ultra after an evaluation that demonstrated its ability to deliver better results than eRide's previous synthesis tool.
eRide has adopted Synopsys' Design Compiler Ultra to design its Opus global positioning system (GPS) integrated circuits (ICs) Opus ICs are low-power ICs that include positioning technology to help wireless carriers minimise their costs
This article was originally published on Electronicstalk on 8 Nov 2007 at 8.00am (UK)
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eRide switched to Design Compiler Ultra after an evaluation that demonstrated its ability to deliver better results than eRide's previous synthesis tool.
"Our previous synthesis solution could not meet the stringent power and area requirements of our next generation Opus ICs".
"In evaluating alternate synthesis technologies, we found Design Compiler Ultra with the DesignWare library to be a superior, reliable synthesis solution easily able to address our complex design challenges", said Allen Chen, Vice President of VLSI Engineering at eRide.
"Advanced synthesis technology coupled with support from the Synopsys team drove our decision to adopt Design Compiler Ultra for our next generation Opus ICs".
The Design Compiler Ultra solution includes topographical technology to accurately predict post-layout timing, area and power during synthesis.
Topographical technology eliminates costly, time consuming iterations between synthesis and layout to significantly reduce design cycle time.
Design Compiler accelerates turnaround time while addressing the complex challenges inherent in complex IC designs.
"Designers rely on Design Compiler's superior technology and quality of results to complete their designs within tight schedules", said Antun Domic, Senior Vice President and General Manager of Synopsys' Implementation Group.
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